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DC-SCI Pin Definition 
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The DC-SCI connector pinout includes the single name (preferred board net name that include functional and directional nomenclature), gold finger lengths, single node usages, voltage, direction, typical usages and dual node usage.
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The contact sequence for each pin indicates the order in which the pins make contact between the HPM and the DC-SCM. The GND pins are required to be long pins or 1st mate. The PRSNT0_N/ PRSNT1_N pins and P12V_AUX pins are required to be short pins or 2nd mate. However, the remaining pins indicated as 2nd mate can be flexibly assigned as long pins/1st mate if dictated by design or DFM requirements.
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Multi-function DC-SCI pins list the functions in order starting with the most typical expected usage.
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When multiple voltages are listed for a signal, they map the respective alternate pin function order.
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DC-SCI Signal Descriptions 
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The following sections provide the signal descriptions of signals through the DC-SCI. 
The signal names are constructed using the notation of:
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 function_(bus source)_(signal source)_(signal destination)_Instance#_Node#_Polarity  
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 Node 1 omits the Node #. Functions with only 1 instance do not include 0. Polarity of active low uses the *_N naming.
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Note: Follow device datasheet recommendations to appropriately terminate un-used signals on the DC-SCM. 
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Abbreviation Definition: 
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Symbol Description
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_N or #  Denotes active low signal
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Input  Input to DC-SCM
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Output  Output from DC-SCM
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InOut At least one of the functions is a bidirectional signal
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CHANGES MADE
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7/27/2022 1.0ver 1.0 release
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3/20/2023Add dual node Alt functions for B39-B42, A51, A52, B9, B10 for TPM
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Add dual node Alt functions for OA8, OA9, OB8, OB9 for SGMII
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5/22/2023Fixed the 2 x TPM assignment in Dual Node (colocation of CS to minimize I2C_I3C Impact)
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Modified the SPI Data IO names for SPI TPM, SPI HPM CTRL and Dual Node TPMs following inclusive naming standards
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Updated the direction of SPI HPM CTRL IO0 and IO1 to match SPI Dual Mode capabilities of this interface
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8/28/2023Relaxed earliest power state on UART0
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9/11/2023Updated earlierst power state for SPI_SCMCNTRL and JTAG and HPM_SCM_IRQ0_N as STBY (not Pre-STBY and not S5)
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9/22/2023Added GPIO directions on NC-SI alt functions
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