1 | Kazakh National Research Technical University named after K.I. Satpayev and Imagination Technologies present a 3-day seminar | |||
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2 | Digital logic and embedded programming in the era of system-on-chip design | |||
3 | October 18-20, 2016 | |||
4 | ||||
5 | Day 1. Electronic industry and the basics of digital design | |||
6 | ||||
7 | The opening | |||
8 | 9:00 - 10:30 | Welcome to the seminar participants from Rector Iskander Beisembetov and Vice Rector Rinat Iskakov | ||
9 | The overview of the electronics industry, main methodologies and organizing the workflow | |||
10 | 10:30 - 10:35 | What is electronic industry? | All areas of electronics ($ 2T), the semiconductor industry ($ 350B), Electronic Design Automation industry - EDA, Semiconductor Intellectual Property industry (Semiconductor IP - SIP) | |
11 | 10:35 - 10:45 | The levels of abstraction in system-on-chip (SoC) design and the corresponding specializations of the design and development engineers | The levels of software, architecture / the processor instruction set, microarchitecture / structure of the pipeline, Register Transfer Level - RTL, gate level, switch / transistor level, physical level | |
12 | 10:45-10:50 | The design and manufacture workflow for the chips | The concept of RTL-to-GDSII flow: the specification, RTL description, simulation and verification, logic synthesis, placement and routing, manufacturing. | |
13 | 10:50 - 11:00 | Economics of the development and manufacturing for different types of chips | Market requirements determine the choice of either Application-Specific Integrated Circuits (ASIC) or Field-Programmable Gate Arrays (FPGA). The balance between cost, flexibility, volume, the initial costs and costs during the life of the project. | |
14 | The review of digital logic and hardware description languages - the foundation of microarchitecture | |||
15 | 11:00 - 11:30 | A very brief introduction to Verilog hardware description language and its comparison with VHDL | Modules, ports, the module hierarchy. Data types, expressions, assignments. Always-blocks and the main statements inside always-blocks. The synthesizable subset and the subsets for simulation and verification. | |
16 | 11:30 - 12:00 | Using Verilog language to design combinational logic | Basic logic gates, basic combinational blocks (multiplexers, decoders), combinational arithmetic circuits (adders), timing (propagation and contamination delays) | |
17 | 12:00 - 13:00 | Lab 1. Creating a combinational circuit that outputs a number or a letter on a seven-segment display" | Working with Xilinx Vivado and Altera Quartus II software for logic synthesis, placement and routing. Configuring FPGA boards, using Digilent Nexys4 DDR and Terasic DE0-CV as examples, implementing a simple digital design using these boards. Each student gets an individual task. | |
18 | 13:00 - 14:00 | Lunch | ||
19 | 14:00 - 14:30 | Using Verilog language for sequential logic design | D-flip-flops, clock period, setup and hold timing constrains, the maximum clock frequency, basic sequential blocks (counters, shift registers) | |
20 | 14:30 - 15:00 | Finite state machines (FSMs) | State diagrams; implementing FSMs in Verilog | |
21 | 15:00 - 15:15 | The bottom line: the rules for writing a correct RTL code in Verilog | Explanations of what kind of problems may occur, for example race conditions, if a designer does not follow those rules | |
22 | 15:15 - 15:30 | Break | ||
23 | 15:30 - 17:00 | Lab 2. Designing a sequential block: counter, shift register or a simple finite state machine | ||
24 | ||||
25 | Day 2. Computer architecture and embedded programming | |||
26 | ||||
27 | 9:00 - 9:30 | Coffee and networking | ||
28 | The review of computer architecture and assembly programming | |||
29 | 9:30 - 9:45 | The difference between the computer architecture and the processor microarchitecture | The computer architecture is a view of a CPU from the programmer's perspective (the instrustion set, the registers visible to the programmer), while microarchitecture is a view of a processor from the perspective of a hardware circuit esigner - the organization of the pipeline, the structure of arithmetic units. | |
30 | 9:45 - 10:00 | A review of the history of computer architecture and microarchitecture, with the discussion of historical developments | The origins of architectures that are currently used in the industry and academia: x86, MIPS, ARM, SPARC, RISC / V | |
31 | 10:00 - 10:45 | Presentation of the course "Connected MCU", developed at the University of North Carolina, in cooperation with Imagination Technologies, Microchip Technology and Digilent (a division of National Instruments) | Connected MCU is a course designed to teach programming microcontrollers to the beginning students. However this course does not stop there: it contains an introduction to broad topics, including the use of real-time operating systems - RTOSes for embedded systems, the elements of computer architecture and performance analysis. | |
32 | 1. Introduction | |||
33 | 2. Software Basics | |||
34 | 3. Peripheral Basics and Port I / O | |||
35 | 4. Basic Concurrency and Interrupts | |||
36 | 5. Analog Interfacing | |||
37 | 6. Timers and Counters | |||
38 | 7. Communications | |||
39 | 8. Other Peripherals | |||
40 | 9. Interfacing with Arduino Shields | |||
41 | 10. Advanced Concurrency | |||
42 | 11. Understanding CPU Throughput Performance | |||
43 | 12. Improving CPU Throughput Performance | |||
44 | 10:45 - 11:00 | Break | ||
45 | 11:00 - 12:00 | A brief introduction to programming in MIPS assembly language | The instructions, operands, registers, constants | |
46 | The concepts of memory address, base register and the offset | |||
47 | Labels, assembly directives for memory allocation and initialization | |||
48 | Arithmetical and logical operations | |||
49 | Conditional branches, direct and indirect jumps | |||
50 | Calling a subroutine, program stack, passing arguments, getting back return values | |||
51 | Exceptions and interrupts | |||
52 | 12:00 - 13:00 | Lab 3. Writing an assembly program that initializes a region of memory with a given sequence of values in a loop | Working with MARS MIPS simulator that models a basic MIPS32 processor at the architectural level. Each student receives an individual task. | |
53 | 13:00 - 14:00 | Lunch | ||
54 | Using microcontrollers to teach software parallelism in embedded systems | |||
55 | 14:00 - 14:15 | Lab 4.1. Getting Started with microcontroller board | Ports, interfacing via GPIO (general-purpose input-output) to buttons and LEDs. Blinking an LED: Lab1_Introduction of Connected MCU. Working with Microchip MPLAB X development environment and PIC32MZ microcontroller. | |
56 | 14:15 - 14:30 | Lab 4.2. Parallel programming using interrupts | A more detailed analysis of the slides "4. Basic Concurrency and Interrupts" "and" "6. Timers and Counters". Demo of the Connected MCU: Demo4_Basic_Concurrency, Demo4_Basic_Concurrency_Interrupts, Demo4_Basic_Concurrency_Tasks | |
57 | 14:30 - 14:45 | Lab 4.3. Parallel programming using interrupts and timers | Flashing LED with Timer: Demo6_Timers_Flashing_LED, LED Scanner with Timer for Delays: Demo6_Basic_Concurrency_Tasks_Timers | |
58 | 14:45 - 15:00 | Break | ||
59 | 15:00 - 16:00 | Explanation how to use Real-Time Operating System (RTOS) for embedded applications | A more detailed analysis of the slides "10. Advanced Concurrency". FreeRTOS is used as an example. | |
60 | The concept of preemptive multitasking: tasks, task status, priority, context switch | |||
61 | Synchronizing tasks with semaphores | |||
62 | Exchanging messages between tasks | |||
63 | Using mutexes to organize mutual exclusion | |||
64 | Using interrupts when running tasks under RTOS | |||
65 | 16:00 - 17:00 | Lab 5: Parallel Programming using interrupts and timers, with RTOS that uses them | LED Scanner with FreeRTOS Tasks: Demo10_Adv_Concurrency_Scan_LEDs; LED Scanner with FreeRTOS Tasks and Semaphores: Demo10_Adv_Concurrency_Scan_LEDs_Sem, Using RTOS Features: Lab10_Adv_Concurrency | |
66 | ||||
67 | Day 3. Processor microarchitecture and designing a system on chip (SoC) | |||
68 | ||||
69 | 9:00 - 9:30 | Coffee and networking | ||
70 | Prototyping SoC in FPGA using MIPSfpga platform for education and research | |||
71 | 9:30-10:00 | MIPSfpga - an introduction | MIPSfpga is a package that contains a processor core with its source code in Verilog. You can modify this core, add new instructions, build multiprocessor systems, change the hardware and software at the same time | |
72 | Comparison of MIPSfpga with Xilinx / ARM Zynq 7000, ARM Design Start, Xilinx MicroBlaze, Xilinx PicoBlaze, Altera NIOS II, RISC / V, OpenRISC , ARM-compatible Amber, OpenSPARC / UltraSPARC T1 / T2, LEON4 | |||
73 | 10:00 - 10:45 | The structure of MIPSfpga+, a variant of MIPSfpga | Board-specific wrappers for synthesis with Xilinx and Altera | |
74 | The structure of board-independent system that consist of the processor core, memory controller and the peripheral input/output devices. Introduction to on-chip buses. | |||
75 | Integrating a peripheral device - a light sensor with SPI serial bus. Comparison of serial buses against each other. | |||
76 | An add-on for loading a software program into the synthesized MIPSfpga system using UART | |||
77 | 10:45 - 11:00 | Break | ||
78 | 11:00 - 11:30 | MIPSfpga demonstration | Simulating MIPSfpga system using ModelSim and Icarus Verilog simulators. Exproring the behavior of the design using waveforms. | |
79 | Synthesizing the system and configuring the FPGA, compiling sample programs and downloading them into the synthesized system using USB-to-UART connector, observing all the components working together. | |||
80 | 11:30 - 13:00 | Lab 6 with MIPSfpga: Light sensor integration | The workshop participants repeat the demonstrations | |
81 | 13:00 - 14:00 | Lunch | ||
82 | Diving deeper into processor: the microarchitecture | |||
83 | 14:00-14:30 | Introduction to the processor microarchitecture | The simplest organization - a single-cycle processor | |
84 | Multicycle CPU - the clock frequency is higher, but each instruction requires more cycles | |||
85 | The pipelined processor organization and the pipeline hazards | |||
86 | 14:30-14:45 | The ways to improve the microarchitecture performance | Resolving pipeline hazards via bypasses / forwarding | |
87 | Pipeline length for different processors as a compromise between the clock frequency and the number of cycles necessary to process an instruiction | Example: a comparison of pipelines in MIPS M5150 and M6250 | ||
88 | Branch target prediction for reducing the number of pipeline flushes in long pipelines when executing conditional branches | Example: Branch target predictor in MIPS 24K | ||
89 | 14:45:15:00 | More advanced ways to improve the performance | Hardware-supported multi-threading | Two ways of multi-threading, illustrated with MIPS interAptiv and MIPS I6400 |
90 | Superscalar processors | Two ways of implementing superscalar processors - in-order, illustrated with MIPS I6400, and out-of-order in MIPS P6600 | ||
91 | Vector extension, or SIMD (single instruction multiple data) | Two examples of vector extensions: full SIMD in MIPS I6400 and MIPS P5600, limited SIMD in DSP ASE implemented in a smaller MIPS M5150 core | ||
92 | 15:00 - 15:15 | Break | ||
93 | 15:15 - 15:45 | Introduction to caches | Direct mapped cache, multy-way set-associate cache. Cache hierarchy. | Example: caches in MIPS microAptiv UP, a microprocessor core used in MIPSfpga package and in Microchip PIC32MZ EF microcontroller |
94 | 15:45 - 16:00 | Multi-core systems | The problem of cache and memory coherence and a solution - MESI protocols and similar approaches | Two ways to implement a coherence manager inside multi-core clusters - an implementation with snooping (using MIPS interAptiv and CM 2.5 as an example) and directory-based implementation (using MIPS I6400 and CM 3.0 as an example) |
95 | 16:00 - 17:00 | Lab 7 with MIPSfpga: a first glance into caches and pipeline forwarding |