imgtec_kazakhstan_2016_10_18_eng
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Kazakh National Research Technical University named after K.I. Satpayev and Imagination Technologies present a 3-day seminar
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Digital logic and embedded programming in the era of system-on-chip design
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October 18-20, 2016
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Day 1. Electronic industry and the basics of digital design
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The opening
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9:00 - 10:30Welcome to the seminar participants from Rector Iskander Beisembetov and Vice Rector Rinat Iskakov
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The overview of the electronics industry, main methodologies and organizing the workflow
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10:30 - 10:35What is electronic industry?All areas of electronics ($ 2T), the semiconductor industry ($ 350B), Electronic Design Automation industry - EDA, Semiconductor Intellectual Property industry (Semiconductor IP - SIP)
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10:35 - 10:45The levels of abstraction in system-on-chip (SoC) design and the corresponding specializations of the design and development engineersThe levels of software, architecture / the processor instruction set, microarchitecture / structure of the pipeline, Register Transfer Level - RTL, gate level, switch / transistor level, physical level
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10:45-10:50The design and manufacture workflow for the chipsThe concept of RTL-to-GDSII flow: the specification, RTL description, simulation and verification, logic synthesis, placement and routing, manufacturing.
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10:50 - 11:00Economics of the development and manufacturing for different types of chipsMarket requirements determine the choice of either Application-Specific Integrated Circuits (ASIC) or Field-Programmable Gate Arrays (FPGA). The balance between cost, flexibility, volume, the initial costs and costs during the life of the project.
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The review of digital logic and hardware description languages - the foundation of microarchitecture
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11:00 - 11:30A very brief introduction to Verilog hardware description language and its comparison with VHDLModules, ports, the module hierarchy. Data types, expressions, assignments. Always-blocks and the main statements inside always-blocks. The synthesizable subset and the subsets for simulation and verification.
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11:30 - 12:00Using Verilog language to design combinational logicBasic logic gates, basic combinational blocks (multiplexers, decoders), combinational arithmetic circuits (adders), timing (propagation and contamination delays)
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12:00 - 13:00Lab 1. Creating a combinational circuit that outputs a number or a letter on a seven-segment display"Working with Xilinx Vivado and Altera Quartus II software for logic synthesis, placement and routing. Configuring FPGA boards, using Digilent Nexys4 DDR and Terasic DE0-CV as examples, implementing a simple digital design using these boards. Each student gets an individual task.
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13:00 - 14:00Lunch
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14:00 - 14:30Using Verilog language for sequential logic designD-flip-flops, clock period, setup and hold timing constrains, the maximum clock frequency, basic sequential blocks (counters, shift registers)
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14:30 - 15:00Finite state machines (FSMs)State diagrams; implementing FSMs in Verilog
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15:00 - 15:15The bottom line: the rules for writing a correct RTL code in VerilogExplanations of what kind of problems may occur, for example race conditions, if a designer does not follow those rules
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15:15 - 15:30Break
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15:30 - 17:00Lab 2. Designing a sequential block: counter, shift register or a simple finite state machine
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Day 2. Computer architecture and embedded programming
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9:00 - 9:30Coffee and networking
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The review of computer architecture and assembly programming
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9:30 - 9:45The difference between the computer architecture and the processor microarchitectureThe computer architecture is a view of a CPU from the programmer's perspective (the instrustion set, the registers visible to the programmer), while microarchitecture is a view of a processor from the perspective of a hardware circuit esigner - the organization of the pipeline, the structure of arithmetic units.
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9:45 - 10:00A review of the history of computer architecture and microarchitecture, with the discussion of historical developmentsThe origins of architectures that are currently used in the industry and academia: x86, MIPS, ARM, SPARC, RISC / V
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10:00 - 10:45Presentation of the course "Connected MCU", developed at the University of North Carolina, in cooperation with Imagination Technologies, Microchip Technology and Digilent (a division of National Instruments)Connected MCU is a course designed to teach programming microcontrollers to the beginning students. However this course does not stop there: it contains an introduction to broad topics, including the use of real-time operating systems - RTOSes for embedded systems, the elements of computer architecture and performance analysis.
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1. Introduction
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2. Software Basics
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3. Peripheral Basics and Port I / O
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4. Basic Concurrency and Interrupts
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5. Analog Interfacing
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6. Timers and Counters
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7. Communications
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8. Other Peripherals
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9. Interfacing with Arduino Shields
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10. Advanced Concurrency
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11. Understanding CPU Throughput Performance
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12. Improving CPU Throughput Performance
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10:45 - 11:00Break
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11:00 - 12:00A brief introduction to programming in MIPS assembly languageThe instructions, operands, registers, constants
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The concepts of memory address, base register and the offset
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Labels, assembly directives for memory allocation and initialization
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Arithmetical and logical operations
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Conditional branches, direct and indirect jumps
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Calling a subroutine, program stack, passing arguments, getting back return values
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Exceptions and interrupts
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12:00 - 13:00Lab 3. Writing an assembly program that initializes a region of memory with a given sequence of values ​​in a loopWorking with MARS MIPS simulator that models a basic MIPS32 processor at the architectural level. Each student receives an individual task.
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13:00 - 14:00Lunch
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Using microcontrollers to teach software parallelism in embedded systems
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14:00 - 14:15Lab 4.1. Getting Started with microcontroller boardPorts, interfacing via GPIO (general-purpose input-output) to buttons and LEDs. Blinking an LED: Lab1_Introduction of Connected MCU. Working with Microchip MPLAB X development environment and PIC32MZ microcontroller.
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14:15 - 14:30Lab 4.2. Parallel programming using interruptsA more detailed analysis of the slides "4. Basic Concurrency and Interrupts" "and" "6. Timers and Counters". Demo of the Connected MCU: Demo4_Basic_Concurrency, Demo4_Basic_Concurrency_Interrupts, Demo4_Basic_Concurrency_Tasks
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14:30 - 14:45Lab 4.3. Parallel programming using interrupts and timersFlashing LED with Timer: Demo6_Timers_Flashing_LED, LED Scanner with Timer for Delays: Demo6_Basic_Concurrency_Tasks_Timers
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14:45 - 15:00Break
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15:00 - 16:00Explanation how to use Real-Time Operating System (RTOS) for embedded applicationsA more detailed analysis of the slides "10. Advanced Concurrency". FreeRTOS is used as an example.
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The concept of preemptive multitasking: tasks, task status, priority, context switch
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Synchronizing tasks with semaphores
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Exchanging messages between tasks
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Using mutexes to organize mutual exclusion
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Using interrupts when running tasks under RTOS
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16:00 - 17:00Lab 5: Parallel Programming using interrupts and timers, with RTOS that uses themLED Scanner with FreeRTOS Tasks: Demo10_Adv_Concurrency_Scan_LEDs; LED Scanner with FreeRTOS Tasks and Semaphores: Demo10_Adv_Concurrency_Scan_LEDs_Sem, Using RTOS Features: Lab10_Adv_Concurrency
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Day 3. Processor microarchitecture and designing a system on chip (SoC)
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9:00 - 9:30Coffee and networking
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Prototyping SoC in FPGA using MIPSfpga platform for education and research
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9:30-10:00MIPSfpga - an introductionMIPSfpga is a package that contains a processor core with its source code in Verilog. You can modify this core, add new instructions, build multiprocessor systems, change the hardware and software at the same time
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Comparison of MIPSfpga with Xilinx / ARM Zynq 7000, ARM Design Start, Xilinx MicroBlaze, Xilinx PicoBlaze, Altera NIOS II, RISC / V, OpenRISC , ARM-compatible Amber, OpenSPARC / UltraSPARC T1 / T2, LEON4
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10:00 - 10:45The structure of MIPSfpga+, a variant of MIPSfpgaBoard-specific wrappers for synthesis with Xilinx and Altera
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The structure of board-independent system that consist of the processor core, memory controller and the peripheral input/output devices. Introduction to on-chip buses.
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Integrating a peripheral device - a light sensor with SPI serial bus. Comparison of serial buses against each other.
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An add-on for loading a software program into the synthesized MIPSfpga system using UART
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10:45 - 11:00Break
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11:00 - 11:30MIPSfpga demonstrationSimulating MIPSfpga system using ModelSim and Icarus Verilog simulators. Exproring the behavior of the design using waveforms.
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Synthesizing the system and configuring the FPGA, compiling sample programs and downloading them into the synthesized system using USB-to-UART connector, observing all the components working together.
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11:30 - 13:00Lab 6 with MIPSfpga: Light sensor integrationThe workshop participants repeat the demonstrations
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13:00 - 14:00Lunch
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Diving deeper into processor: the microarchitecture
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14:00-14:30Introduction to the processor microarchitectureThe simplest organization - a single-cycle processor
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Multicycle CPU - the clock frequency is higher, but each instruction requires more cycles
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The pipelined processor organization and the pipeline hazards
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14:30-14:45The ways to improve the microarchitecture performanceResolving pipeline hazards via bypasses / forwarding
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Pipeline length for different processors as a compromise between the clock frequency and the number of cycles necessary to process an instruictionExample: a comparison of pipelines in MIPS M5150 and M6250
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Branch target prediction for reducing the number of pipeline flushes in long pipelines when executing conditional branchesExample: Branch target predictor in MIPS 24K
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14:45:15:00More advanced ways to improve the performanceHardware-supported multi-threadingTwo ways of multi-threading, illustrated with MIPS interAptiv and MIPS I6400
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Superscalar processorsTwo ways of implementing superscalar processors - in-order, illustrated with MIPS I6400, and out-of-order in MIPS P6600
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Vector extension, or SIMD (single instruction multiple data)Two examples of vector extensions: full SIMD in MIPS I6400 and MIPS P5600, limited SIMD in DSP ASE implemented in a smaller MIPS M5150 core
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15:00 - 15:15Break
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15:15 - 15:45Introduction to cachesDirect mapped cache, multy-way set-associate cache. Cache hierarchy.Example: caches in MIPS microAptiv UP, a microprocessor core used in MIPSfpga package and in Microchip PIC32MZ EF microcontroller
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15:45 - 16:00Multi-core systemsThe problem of cache and memory coherence and a solution - MESI protocols and similar approaches Two ways to implement a coherence manager inside multi-core clusters - an implementation with snooping (using MIPS interAptiv and CM 2.5 as an example) and directory-based implementation (using MIPS I6400 and CM 3.0 as an example)
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16:00 - 17:00
Lab 7 with MIPSfpga: a first glance into caches and pipeline forwarding
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oct 5 2016