| A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | AA | AB | AC | AD | AE | AF | AG | AH | AI | AJ | AK | AL | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | Lower Memory Address | Higher Memory Address | ||||||||||||||||||||||||||||||||||||
2 | Avail | Fmt | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
3 | Shift by Immediate | v6-M | B | 0 | 0 | 0 | opcode | immediate | Rm | Rd | ||||||||||||||||||||||||||||
4 | Add/Subtract Register | v6-M | I | 0 | 0 | 0 | 1 | 1 | 0 | opc | Rm | Rn | Rd | = | Available in ARMv6-M and up (e.g. M0, M0+, M1) | |||||||||||||||||||||||
5 | Add/Subtract Immediate | v6-M | K | 0 | 0 | 0 | 1 | 1 | 1 | opc | immediate | Rn | Rd | = | Available in ARMv7-M and up (e.g. M3) | |||||||||||||||||||||||
6 | Add/subtract/move/compare immediate | v6-M | D | 0 | 0 | 1 | opcode | Rd | immediate | = | Available in ARMv7E-M (DSP extensions, e.g. M4) | |||||||||||||||||||||||||||
7 | Data Processing Register | v6-M | Q | 0 | 1 | 0 | 0 | 0 | 0 | opcode | Rm | Rd | ||||||||||||||||||||||||||
8 | Special Data Processing | v6-M | N | 0 | 1 | 0 | 0 | 0 | 1 | opcode | Rd[3] | Rm | Rd[2:0] | For floating point extensions (e.g. M4F), see FPv4-SP tab. | ||||||||||||||||||||||||
9 | Branch / Exchange | v6-M | P | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | L | Rm | (0) | (0) | (0) | ||||||||||||||||||||||
10 | Load literal (PC-relative) | v6-M | E | 0 | 1 | 0 | 0 | 1 | Rd | immediate | This depicts the complete set of binary instruction encodings available in M-profile processors as of this writing (summer 2014). This is derived from various public sources and my own experience, and is intended to fill a serious gap in ARM's documentation (they have not published a table of this form). Related instructions are collapsed into a single row iff their operand fields and operation encoding can be described compactly, and they share standard assembly syntax. I've derived names for opcode bits where such names are clear. This encoding is very complex, for historical and space-efficiency reasons, so every pattern we can find helps. Cells with a black triangle in the corner have notes. Mouse over the cell to view the notes. If you're writing an assembler or disassembler, have a look at the format tabs below -- they provide a higher-level overview of the encodings. Finally, if you're using an M0 or just getting started on an M3/M4, consider sticking to the v6m instruction set described on the next tab. | |||||||||||||||||||||||||||
11 | Load/store register indexed | v6-M | J | 0 | 1 | 0 | 1 | opcode | Rm | Rn | Rd | |||||||||||||||||||||||||||
12 | Load/store word/byte displacement | v6-M | C | 0 | 1 | 1 | B | L | immediate | Rn | Rd | |||||||||||||||||||||||||||
13 | Load/store halfword displacement | v6-M | C | 1 | 0 | 0 | 0 | L | immediate | Rn | Rd | |||||||||||||||||||||||||||
14 | Load/store SP-relative displacement | v6-M | E | 1 | 0 | 0 | 1 | L | Rd | immediate | ||||||||||||||||||||||||||||
15 | Address generation from PC or SP | v6-M | F | 1 | 0 | 1 | 0 | SP | Rd | immediate | ||||||||||||||||||||||||||||
16 | Add to / subtract from SP | v6-M | O | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | S | immediate | |||||||||||||||||||||||||
17 | Compare and branch if (non) zero | v7-M | T | 1 | 0 | 1 | 1 | N | 0 | d6 | 1 | disp[5:1] | Rn | |||||||||||||||||||||||||
18 | Extend byte / halfword | v6-M | Q | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | U | B | Rm | Rd | |||||||||||||||||||||||
19 | PUSH and POP | v6-M | L | 1 | 0 | 1 | 1 | L | 1 | 0 | M | reglist | ||||||||||||||||||||||||||
20 | CPS | v6-M | R | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | E | (0) | (0) | I | F | |||||||||||||||||||
21 | Reverse Bytes | v6-M | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | S | H | Rm | Rd | |||||||||||||||||||||||
22 | Breakpoint | v6-M | M | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | immediate | ||||||||||||||||||||||||||
23 | If-Then | v7-M | U | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | first | mask | |||||||||||||||||||||||||
24 | Hint | v6-M | S | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | opcode | 0 | 0 | 0 | 0 | ||||||||||||||||||||||
25 | Load/store multiple | v6-M | G | 1 | 1 | 0 | 0 | L | Rn | reglist | ||||||||||||||||||||||||||||
26 | Conditional branch | v6-M | A | 1 | 1 | 0 | 1 | cc | destination | |||||||||||||||||||||||||||||
27 | Supervisor Call | v6-M | M | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | immediate | ||||||||||||||||||||||||||
28 | Unconditional Branch | v6-M | H | 1 | 1 | 1 | 0 | 0 | destination | |||||||||||||||||||||||||||||
29 | ||||||||||||||||||||||||||||||||||||||
30 | Branch and Link | v6-M | 1 | 1 | 1 | 1 | 1 | 0 | S | disp[21:12] | 1 | L | J2 | 1 | J1 | disp[11:1] | ||||||||||||||||||||||
31 | MSR | v6-M | 2 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | (0) | Rn | 1 | 0 | (0) | 0 | mask | (0) | (0) | SYSm | ||||||||||||||
32 | MRS | v6-M | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | (0) | (1) | (1) | (1) | (1) | 1 | 0 | (0) | 0 | Rd | SYSm | |||||||||||||
33 | Barrier | v6-M | 4 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | type | scope | |||||||||
34 | ||||||||||||||||||||||||||||||||||||||
35 | Load / Store multiple | v7-M | 9 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | order | 0 | W | L | Rn | reglist | ||||||||||||||||||||||
36 | Load / Store Double | v7-M | 10 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | P | U | 1 | W | L | Rn | Rt | Rt2 | imm8 | Either P or W must be set. | ||||||||||||||||||
37 | Load / Store Exclusive Word | v7-M | 25 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | L | Rn | Rt | (1) | (1) | (1) | (1) | imm8 | Special case of double encoding where P==W==0 | |||||||||||||||
38 | Load / Store Exclusive Byte / Halfword | v7-M | 31 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | L | Rn | Rt | (1) | (1) | (1) | (1) | 0 | 1 | 0 | H | (1) | (1) | (1) | (1) | |||||||||
39 | Table Branch Byte / Halfword | v7-M | 32 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Rn | (1) | (1) | (1) | (1) | (0) | (0) | (0) | (0) | 0 | 0 | 0 | H | Rm | |||||||||
40 | Data processing, shifted register | v7-M | 16 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | opcode | S | Rn | (0) | sh[4:2] | Rd | sh[1:0] | type | Rm | |||||||||||||||||||
41 | Pack Halfwords | v7E-M | 20 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | (0) | Rn | (0) | sh[4:2] | Rd | sh[1:0] | tb | (0) | Rm | ASR #0 cannot be encoded; operands must be flipped! | ||||||||||||||
42 | Data processing, modified immediate | v7-M | 6 | 1 | 1 | 1 | 1 | 0 | I | 0 | opcode | S | Rn | 0 | imm3 | Rd | imm8 | |||||||||||||||||||||
43 | Data processing, plain 12-bit immediate | v7-M | 7 | 1 | 1 | 1 | 1 | 0 | i11 | 1 | 0 | opcode | 0 | Rn | 0 | imm[10:8] | Rd | imm[7:0] | ||||||||||||||||||||
44 | 16-bit immediate moves | v7-M | 8 | 1 | 1 | 1 | 1 | 0 | i11 | 1 | 0 | T | 1 | 0 | 0 | imm[15:12] | 0 | imm[10:8] | Rd | imm[7:0] | ||||||||||||||||||
45 | Word saturation | v7-M | 15 | 1 | 1 | 1 | 1 | 0 | (0) | 1 | 1 | U | 0 | type | 0 | Rn | 0 | sh[4:2] | Rd | sh[1:0] | (0) | sat | ||||||||||||||||
46 | Halfword pair saturation | v7E-M | 30 | 1 | 1 | 1 | 1 | 0 | (0) | 1 | 1 | U | 0 | 1 | 0 | Rn | 0 | 0 | 0 | 0 | Rd | 0 | 0 | (0) | (0) | sat | ASR 0 version of word saturation | |||||||||||
47 | Bitfield extraction | v7-M | 21 | 1 | 1 | 1 | 1 | 0 | (0) | 1 | 1 | U | 1 | 0 | 0 | Rn | 0 | lsb[4:2] | Rd | lsb[1:0] | (0) | widthm1 | ||||||||||||||||
48 | Bitfield insertion | v7-M | 22 | 1 | 1 | 1 | 1 | 0 | (0) | 0 | 1 | 1 | 1 | 0 | 0 | Rn | 0 | lsb[4:2] | Rd | lsb[1:0] | (0) | msbit | ||||||||||||||||
49 | Conditional branch | v7-M | 5 | 1 | 1 | 1 | 1 | 0 | S | cc | disp[17:12] | 1 | 0 | J2 | 0 | J1 | disp[11:1] | |||||||||||||||||||||
50 | Hints | v7-M | 35 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | (1) | (1) | (1) | (1) | 1 | 0 | (0) | 0 | (0) | 0 | 0 | 0 | hint kind | ||||||||||
51 | Barriers | v7-M | 34 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | (1) | (1) | (1) | (1) | 1 | 0 | (0) | 0 | (1) | (1) | (1) | (1) | 0 | 1 | barrier | option | |||||||
52 | CLREX | v7-M | 35 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | (1) | (1) | (1) | (1) | 1 | 0 | (0) | 0 | (1) | (1) | (1) | (1) | 0 | 0 | 1 | 0 | (1) | (1) | (1) | (1) | |||
53 | Load/Store single, wide displacement | v7-M | 18 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | S | 1 | size | L | Rn | Rt | imm12 | |||||||||||||||||||||
54 | Load/Store single, immediate | v7-M | 19 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | S | 0 | size | L | Rn | Rt | 1 | P | U | W | imm8 | Special combination P U !W indicates unprivileged access. | ||||||||||||||||
55 | Load/Store unprivileged | v7-M | 25 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | S | 0 | size | L | Rn | Rt | 1 | 1 | 1 | 0 | imm8 | |||||||||||||||||
56 | Load/Store single, register | v7-M | 26 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | S | 0 | size | L | Rn | Rt | 0 | 0 | 0 | 0 | 0 | 0 | shift | Rm | ||||||||||||||
57 | Register shift | v7-M | 14 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | type | S | Rn | 1 | 1 | 1 | 1 | Rd | 0 | 0 | 0 | 0 | Rm | |||||||||||||
58 | Extend | v7-M | 33 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | opcode | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | Rd | 1 | (0) | rotate | Rm | ||||||||||||
59 | Extend and Add | v7E-M | 27 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | opcode | Rn | 1 | 1 | 1 | 1 | Rd | 1 | (0) | rotate | Rm | |||||||||||||||
60 | Parallel add/subtract. | v7E-M | 28 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | opcode | Rn | 1 | 1 | 1 | 1 | Rd | 0 | U | mode | Rm | |||||||||||||||
61 | Saturating word operations, SEL | v7E-M | 28 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | opc | 0 | Rn | 1 | 1 | 1 | 1 | Rd | 1 | 0 | opcode | Rm | |||||||||||||
62 | Reversal, CLZ | v7-M | 29 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | opc | 1 | Rm | 1 | 1 | 1 | 1 | Rd | 1 | 0 | opcode | Rm | |||||||||||||
63 | Multiply | v7-M | 28 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | Rn | 1 | 1 | 1 | 1 | Rd | 1 | 0 | 0 | 0 | Rm | ||||||||||||
64 | Multiply accumulate/subtract | v7-M | 23 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Ra | Rd | 1 | 0 | 0 | S | Rm | |||||||||||||||
65 | Extended 32/16-bit multiplication | v7E-M | 28 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | opcode | Rn | 1 | 1 | 1 | 1 | Rd | 1 | 0 | opcode | Rm | |||||||||||||||
66 | Extended 32/16-bit multiply/accumulate | v7E-M | 23 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | opcode | Rn | Ra | Rd | 1 | 0 | opcode | Rm | ||||||||||||||||||
67 | Long Multiply | v7-M | 24 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | A | U | 0 | Rn | RdLo | RdHi | 0 | 0 | 0 | 0 | Rm | |||||||||||||||
68 | Division | v7-M | 28 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | U | 1 | Rn | (1) | (1) | (1) | (1) | Rd | 1 | 1 | 1 | 1 | Rm | ||||||||||||
69 | Long Multiply Extended | v7E-M | 24 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | opcode | Rn | RdLo | RdHi | opcode | Rm | ||||||||||||||||||||
70 | Coprocessor Dual Register Move | v7-M | 17 | 1 | 1 | 1 | C | 1 | 1 | 0 | 0 | 0 | 1 | 0 | R | Rt2 | Rt | coproc | opcode | CRm | These are the general, coprocessor-agnostic forms and are rarely used. Typically an assembler will define coprocessor-specific mnemonics and syntax that generate these forms. See the FPv4-SP encoding for one example (and the only example thus far supported on M-profile processors). | |||||||||||||||||
71 | Coprocessor Data Processing | v7-M | 12 | 1 | 1 | 1 | C | 1 | 1 | 1 | 0 | opc1 | CRn | CRd | coproc | opc2 | 0 | CRm | ||||||||||||||||||||
72 | Coprocessor Single Register Move | v7-M | 13 | 1 | 1 | 1 | C | 1 | 1 | 1 | 0 | opc1 | R | CRn | Rt | coproc | opc2 | 1 | CRm | |||||||||||||||||||
73 | Load/Store Coprocessor | v7-M | 11 | 1 | 1 | 1 | C | 1 | 1 | 0 | P | U | N | W | L | Rn | CRd | coproc | imm8 | |||||||||||||||||||