DLD UNIT 3,4,5 QUIZ QUESTIONS AND ANSWERS

	A	B	C	D	E	F	G	H	I
1	UNIT-3
2	1	2	3	Code conversion circuits mostly uses	AND-OR gates	AND gates	OR gates	XOR gates	1
3	2	2	3	Full Adder combinational circuits has 3 inputs and	2 outputs	1 output	3 outputs	None	4
4	3	2	3	The NOR function is the dual of	AND function	OR function	XOR function	NAND function	4
5	4	2	3	Designing combinational circuit involves	4 steps	5 steps	6 steps	8 steps	3
6	5	2	3	Half adder circuits requires two binary	Inputs	Outputs	Digits	Both a and b	4
7	6	2	3	The subtraction of two binary numbers is accomplished by taking comple-	output	subtract or	Minuend	remainder	3
8	7	2	3	Circuits that employs memory elements in addition to gates is called	combinational circuit	sequential circuit	combinational sequence	series	2
9	8	2	3	When both inputs are 1, the output of XOR is	1	0	x	10	2
10	9	2	3	The simplified expression of full adder carry is	c=xy+xz+yz	c=xy+xz	c=xy+yz	c=x+y+z	1
11	10	2	3	Practical design procedure have some	gates	circuits	constraints	protocols	3
12	11	2	3	Half subtractor have an output to specify that 1 has been?	complemented	borrowed	carried	primed	2
13	12	2	3	Logic gates takes input signals and generates signals to	within gate	input	output	Both a and b	3
14	13	2	3	For code conversion how many bits are required for BCD input and Excess outputs?	3 inputs and 2 outputs	4 inputs and 4 outputs	4 inputs and 3 outputs	None	2
15	14	2	3	Two bit subtraction is done by	Demultiplexer	Multiplexer	full subtract	half subtract	4
16	15	2	3	Dual of the NAND function is	AND function	OR function	NOR function	NAND function	3
17	16	2	3	Besides NAND gate universal gate is	AND gate	OR gate	NOR gate	XOR gates	3
18	17	2	3	The most basic arithmetic function is	addition	subtraction	multiplication	division	1
19	18	2	3	Variable in Boolean expressions can be expressed as	primed	unprimed	even	Both a and b	4
20	19	2	3	Circuit that is said to be universal gate is	AND	OR	NAND	XOR	3
21	20	2	3	The connection from output to one of input gate is	undefined	shifted	feedback	wire	3
22	21	2	3	In NAND logic analysis procedure application requires repeated appli-	truth table	feedback theorem	demorgan's theorem	K-map	3
23	22	2	3	Circuits whose output depends on directly present input is called	combinational circuit	sequential circuit	combinational sequence	series	1
24	23	2	3	Full subtract circuits have	3 inputs and 2 outputs	1 input and 1 output	both a and b	None	1
25	24	2	3	In designing a combinational circuits, truth table defines the relationship	logical circuit	input	output	input and output	4
26	25	2	3	The most significant bit of arithmetic addition is called	overflow	carry	output	zero bit	2
27	26	2	3	Flip flop are constructed using	AND gate	OR gate	NAND gate	NOR gate	3
28	27	2	3	Two bit addition is done by	ripple carry adder	carry sum adder	full adder	half adder	4
29	28	2	3	AND gates are converted to NAND gates using	invert OR	AND invert	NAND invert	Both a and b	2
30	29	2	3	In don't cares map input are marked by	0	1	star	X	4
31	30	2	3	OR operation is achieved through a NAND gate with Additional	AND gates	OR gates	XOR gates	Inverters	3
32	UNIT-4
33	1	2	4	By default counters are incremented by	1	2	3	4	1
34	2	2	4	The simplest registers only consists of	counter	EPROM	latch	flip-flop	4
35	3	2	4	Three decade counter would have	2 BCD counters	3 BCD counters	4 BCD counters	5 BCD counters	2
36	4	2	4	A decimal counter has	5 states	10 states	15 states	20 states	2
37	5	2	4	Memory that is called a read write memory is	ROM	EPROM	RAM	Registers	3
38	6	2	4	A register that is capable for shifting its binary information either to left or the Right side is called as	Latch register	flip-flops	binary register	Shift Register	2
39	7	2	4	Ripple counters are also called	SSI counters	asynchronous counters	synchronous counters	VLSI counters	2
40	8	2	4	Transformation of information into registers is called	loading	gated latch	latch	storing	1
41	9	2	4	Binary counter that count incrementally and decremently is called	up-down counter	LSI counters	down counter	up counter	1
42	10	2	4	Shift registers having four bits will enable the shift control signal for	2 clock pulses	3 clock pulses	4 clock pulses	5 clock pulses	3
43	11	2	4	A group of binary cells is called	counter	register	latch	flip-flop	2
44	12	2	4	Synchronous counter is a type of	SSI counters	LSI counters	MSI counters	VLSI counters	3
45	13	2	4	BCD counter is also known as	parallel counter	decade counter	synchronous counter	VLSI counter	2
46	14	2	4	A 8bit flip-flop has	2binary cells	4binary cells	6binary cells	8binary cells	4
47	15	2	4	Parallel load transfer is done in	1 cycle	2 cycle	3 cycle	4 cycle	1
48	16	2	4	A counter with parallel load can be used to generate number of	Latches	Flip-flops	registers	counter sequences	2
49	17	2	4	Ripple counter cannot be described by	Boolean equation	clock duration	graph	flow chart	1
50	18	2	4	Time between the clock pulses are called	bit duration	clock duration	duration	bit time	4
51	19	2	4	Parallel loading is done with	1 cycle	2 cycle	3 cycle	4 cycle	1
52	20	2	4	The word time signals can be generated by means of a counter that	reset signals	Pluses	latches	flip-flops	2
53	21	2	4	BCD counter counts from	0 to 5	1 to 5	0 to 9	1 to 9	3
54	22	2	4	J=K=0 will make flip-flops	changed	reversed	unchanged	stopped	3
55	23	2	4	Special type of registers are	latch	flip-flop	counters	memory	3
56	24	2	4	Flip-flops in registers are	present	level triggered	edge triggered	not present	3
57	25	2	4	Down counter decrement the value by	1	2	3	4	1
58	26	2	4	Register giving response to pulse duration is called	latch	gated latch	counters	flip-flop	2
59	27	2	4	8bit information can be stored in	2registers	4registers	6registers	8registers	4
60	28	2	4	BCD stands for	binary counter design	binary counter decimal	binary coded design	binary coded decimal	4
61	29	2	4	PLA stands for	programmable lead array	programmable logic agency	predicted logic array	programmable logic array	4
62	30	2	4	Circular shift register is called	SSI counters	LSI counters	ring counter	ripple counter	3
63	UNIT-5
64	1	2	5	A circuit that converts n inputs to 2^n outputs is called	encoder	decoder	comparator	carry look ahead	2
65	2	2	5	All the comparisons made by comparator is done using	1circuit	2circuits	3circuits	4circuits	1
66	3	2	5	A BCD adder is a circuit that adds two BCD digits in parallel and produces	hexadecimal code	binary code	BCD code	decimal code	2
67	4	2	5	Encoders are made by three	AND gate	OR gate	NAND gate	XOR gate	2
68	5	2	5	Small Scale Integrated (SSI) circuit has several independent gates about	12 or 14 pins	13 or 14 pins	14 or 16 pins	15 or 16 pins	3
69	6	2	5	PROM stands for	Permanent Read Only Memory	Portable Read Only Memory	Programmable Read Only Memory	Plugin Read Only Memory	3
70	7	2	5	PLD stands for	portable large device	portable logic device	programmable large device	programmable logic device	4
71	8	2	5	A binary parallel adder produces the arithmetic sum in	serial	parallel	sequence	both a and b	2
72	9	2	5	Decoder is a	combinational circuit	sequential circuit	complex circuit	gate	1
73	10	2	5	ROM is a	non volatile memory	secondary memory	volatile memory	small memory	1
74	11	2	5	The basic component used in the design of VLSI is?	NOR Gate	AND Gate	XOR Gate	Gate array	4
75	12	2	5	The full adder forms the sum of	2bits	3bits	4bits	5bits	1
76	13	2	5	Rom can be programmed in	2 ways	3 ways	4 ways	5 ways	1
77	14	2	5	If two numbers are not equal then binary variable will be	0	1	a	b	1
78	15	2	5	EPROM stands for	Electrical Programmable Read Only Memory	Electrical Portable Read Only Memory	Erasable Programmable Read Only Memory	Erasable Portable Read Only Memory	3
79	16	2	5	Several combinational circuits that are used in designing of digital sys-	high cost circuit	MSI components	complicated circuits	simplified circuits	2
80	17	2	5	The subtraction of binary numbers can be done conveniently with	high cost circuit	low cost circuits	complements	borrows	3
81	18	2	5	Carry generator in full adder has expression i.e.	G=AB	G=A+B	G=A-B	G=AB	1
82	19	2	5	2^9 nine input circuit would have	32 entries	128 entries	256 entries	512 entries	4
83	20	2	5	One that is not the outcome of magnitude comparator is	a>b	a-b	a<b	a=b	2
84	21	2	5	IC decoders are made with	AND gate	OR gate	NAND gate	XOR gate	3
85	22	2	5	The sum of two n-bit binary numbers can be generated as	Directly	Serial and Parallel	Serially	None	3
86	23	2	5	The ROM is a device that includes both the decoder and?	encoder	Multiplexer	OR Gates	None	3
87	24	2	5	4 to 1 mux would have	2inputs	3inputs	4inputs	5inputs	3
88	25	2	5	Discrete quantities of information are represented in digital system with	Uni code	ASCII code	Binary Code	Octal code	2
89	26	2	5	MSI stands for	small scale integration	medium scale integration	mask scale integration	median scale integration	2
90	27	2	5	The limiting factor on a speed of parallel adder is	input delay	carry propagation delay	input propagation delay	output delay	2
91	28	2	5	A multiplexer is also called as a	Coder	parallel adder	Data selector	NOR gate	3
92	29	2	5	BCD adder can be constructed with 3 Integrated circuits (IC) packages	2bits	3bits	4bits	5bits	3
93	30	2	5	The two input multiplexer would have	1 select line	2 select lines	4 select lines	3 select lines	1
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