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MASC UCSC HDLEval TestBench
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This document details the test bench for HDL Eval project for Micro Architecture @ Santa Cruz (MASC)
University of California, Santa Cruz

Author : Ashwin Bardhwaj (UC Berkeley) ashbardh@berkeley.edu
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Latest Build 0.0.1
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Release DateAugust 21 2024
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Note for the readerThe goal of this project is to create large-scale Verilog programs in order to benchmark the capability of LLMs to develop HDL Verilog code. Throughout this project, I have created 3 of these large Verilog testbenches called: 3-Stage-RISC V processor, Gameboy Emulator, and Sorts. The benchmark programs will lose their effectiveness if LLMs such as ChatGPT scrape over Github repos and learn from them. As a result, the code itself cannot be made public due to LLM scraping on repositories. Therefore, this file will cover the test report for all 3 of these projects.

*If you are interested in the code, please contact me (Ashwin Bardhwaj) at ashbardh@berkeley.edu
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SummaryThis test report contains two sections for each project. Tabs labeled {Project Name} are the Verilog modules run against ChatGPT 3 turbo and 4o. The exact instruction used for the module as well as the result of testing has been recorded. Tabs labeled "{Project Name}_Verify" are the test cases used for that project to ensure its validity and correctness.


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