Xcondensed Encoding

	A	B	C	D	E	F	G	H	I	J	K	L
1	Nr	spec	CV1.9 analog (color see notes)	C/Xc	5bit-opcode	type	instruction
2	1	I	shsp/swsp/sdsp/sqsp	CXc	sxsp/sys	store mem	sxsp	5rs1*	6imm		s[hwdq] rs1 (imm<<x)(sp)
3	2
4	3	I64	swsp	CXc	swsp	store mem	swsp	5rs1*	6imm		sw rs1 (imm<<2)(sp)	Is this one worth it?
5	4	reserved			swsp			zero	6imm
6	5
7	6	I	lhsp/lwsp/ldsp/lqsp	CXc	lxsp	load mem	lxsp	5rd*	6imm		l[hwdq] rd (imm<<x)(sp)
8	7	reserved			lxsp			zero	6imm
9	8
10	9	I64	lwsp	CXc	lwsp	load mem	lwsp	5rd*	6imm		lw rd (imm<<2)(sp)	Is this one worth it
11	10	reserved			lwsp			zero	6imm
12	11
13	12	I	lh/lw/ld/lq	CXc	lx	load mem	lx	3rd	3rs1	5imm	l[hwdq] rd (imm<<x)(rs1)
14	13
15	14	I64	lw	CXc	lw	load mem	lw	3rd	3rs1	5imm	lw rd (imm<<2)(rs1)
16	15
17	16	I	sh/sw/sd/sq	CXc	sx	store mem	sx	3rs1	3rs2	5imm	s[hwdq] rs1 (imm<<x)(rs2)
18	17
19	18	I64	sw	CXc	sw	store mem	sw	3rs1	3rs2	5imm	sw rs1 (imm<<2)(rs2)
20	19
21	20	I		Xc	load	load mem	l.b	0	3rd	3rs1	lb rd 0(rs1)
22	21	I32		Xc	load	load mem	l.h	1	3rd	3rs1	lh rd 0(rs1)
23	22	I		Xc	load	load mem	l.bu	2	3rd	3rs1	lbu rd 0(rs1)
24	23	I32		Xc	load	load mem	l.hu	3	3rd	3rs1	lhu rd 0(rs1)
25	24	I64		Xc	load	load mem	l.wu	4	3rd	3rs1	lwu rd 0(rs1)
26	25	reserved			load			5
27	26	A		Xc	load	amo	amo.l.x.aqrl	6	3rd	3rs1	amo.add rd rs1 zero
28	27	A64		Xc	load	amo	amo.l.w.aqrl	7	3rd	3rs1	amo.addw rd rs1 zero
29	28	S	flw/flspw (-)	CXc	load	fp	l.fw0	8	3frd	3rs1	flw 3frd (0<<2)(3rs1)
30	29	S	flw/flspw (-)	CXc	load	fp	l.fw1	9	3frd	3rs1	flw 3frd (1<<2)(3rs1)
31	30	S	flw/flspw (-)	CXc	load	fp	l.fw2	10	3frd	3rs1	flw 3frd (2<<2)(3rs1)
32	31	S	flw/flspw (-)	CXc	load	fp	l.fw3	11	3frd	3rs1	flw 3frd (3<<2)(3rs1)
33	32	D	fld/flspd (-)	CXc	load	fp	l.fd0	12	3frd	3rs1	fld 3frd (0<<3)(3rs1)
34	33	D	fld/flspd (-)	CXc	load	fp	l.fd1	13	3frd	3rs1	fld 3frd (1<<3(3rs1)
35	34	D	fld/flspd (-)	CXc	load	fp	l.fd2	14	3frd	3rs1	fld 3frd (2<<3)(3rs1)
36	35	D	fld/flspd (-)	CXc	load	fp	l.fd3	15	3frd	3rs1	fld 3frd (3<<3)(3rs1)
37	36	I		Xc	load	alu	seqz	16	3rd	3rs1	sltui rd rs1 1	also serves as boolnot. snez can be done in two instructions as li rd 0; sltu rd rd rs2 and snez sltu rd zero rs1 got the wrong ordering of rs1 and rs2 :-(
38	37	I		Xc	load	alu	sltz	17	3rd	3rs1	slt rd rs1 zero	equivalent: srai rd rs1 -1
39	38	I		Xc	load	alu	slez	18	3rd	3rs1	slti rd rs1 1	alternatively have a sgtz: sltz rd zero rs1 but this has the wrong ordering of rs1 and rs2
40	39	I		Xc	load	alu	not	19	3rd	3rs1	xori rd rs1 -1
41	40	I		Xc	load	jump	jalr	20	3rd	3rs1	jalr rd rs1 0x0
42	41	reserved			load			21			andi0xffffffff rd rs1 --> "andi rd rd 0xffffffff"?
43	42	reserved			load			22
44	43	reserved			load			23
45	44	A		Xc	load	amo	lr.x	24	3rd	3rs1	lr.wdq rd 0(rs1)
46	45	A		Xc	load	amo	lr.x.aq	25	3rd	3rs1	lr.wdq.aq rd 0(rs1)
47	46	A		Xc	load	amo	lr.x.rl	26	3rd	3rs1	lr.wdq.rl rd 0(rs1)
48	47	A		Xc	load	amo	lr.x.aqrl	27	3rd	3rs1	lr.wdq.aqrl rd 0(rs1)
49	48	A64		Xc	load	amo	lr.w	28	3rd	3rs1	lr.w rd 0(rs1)
50	49	A64		Xc	load	amo	lr.w.aq	29	3rd	3rs1	lr.w.aq rd 0(rs1)
51	50	A64		Xc	load	amo	lr.w.rl	30	3rd	3rs1	lr.w.rl rd 0(rs1)
52	51	A64		Xc	load	amo	lr.w.aqrl	31	3rd	3rs1	lr.w.aqrl rd 0(rs1)
53	52
54	53	I		Xc	store	store mem	s.b	0	3rs1	3rs2	sb rs1 0(rs2)
55	54	I32		Xc	store	store mem	s.h	1	3rs1	3rs2	sh rs1 0(rs2)
56	55	reserved			store			4	3rs1	3rs2
57	56	reserved			store			5	3rs1	3rs2	swap 3rsd1 5rsd2?
58	57	reserved			store			6	3rs1	3rs2
59	58	reserved			store			7	3rs1	3rs2
60	59	A		Xc	store	amo	amo.s.x.aqrl	3	3rs1	3rs2	amo.swap zero rs1 rs2
61	60	A64		Xc	store	amo	amo.s.w.aqrl	2	3rs1	3rs2	amo.swapw zero rs1 rs2	Note order of address and value reversed from s.b and s.h
62	61	S	fsw/fsspw (-)	CXc	store	fp	s.fw0	8	3frs1	3rs2	fsw (0<<2)(rs2) frs1
63	62	S	fsw/fsspw (-)	CXc	store	fp	s.fw1	9	3frs1	3rs2	fsw (1<<2)(rs2) frs1
64	63	S	fsw/fsspw (-)	CXc	store	fp	s.fw2	10	3frs1	3rs2	fsw (2<<2)(rs2) frs1
65	64	S	fsw/fsspw (-)	CXc	store	fp	s.fw3	11	3frs1	3rs2	fsw (3<<2)(rs2) frs1
66	65	D	fsd/fsspd (-)	CXc	store	fp	s.fd0	12	3frs1	3rs2	fsd (0<<3)(rs2) frs1
67	66	D	fsd/fsspd (-)	CXc	store	fp	s.fd1	13	3frs1	3rs2	fsd (1<<3)(rs2) frs1
68	67	D	fsd/fsspd (-)	CXc	store	fp	s.fd2	14	3frs1	3rs2	fsd (2<<3)(rs2) frs1
69	68	D	fsd/fsspd (-)	CXc	store	fp	s.fd3	15	3frs1	3rs2	fsd (3<<3)(rs2) frs1
70	69	A		Xc	store	amo	amo.swap.x.aqrl	16	3rsd	3rs2	amo.swapwdq rsd rsd (rs2)	Use amo's for memory mapped CSR's e.g. mapped at 0x0 assuming x =3: csrwr rd rd CSR --> lui a5 CSR[11: 9 ]; add6i a5 CSR[8:3]; addi[2:0]000 slli a5 x; amo.swap.x.aqrl rd a5
71	70	A		Xc	store	amo	amo.or.x.aqrl	17	3rsd	3rs2	amo.or wdq rsd rsd (rs2)
72	71	A		Xc	store	amo	amo.and.x.aqrl	18	3rsd	3rs2	amo.andwdq rsd rsd (rs2)
73	72	A		Xc	store	amo	amo.add.x.aqrl	19	3rsd	3rs3	amo.addwdq rsd rsd (rs2)
74	73	A64		Xc	store	amo	amo.swap.w.aqrl	24	3rsd	3rs2	amo.swapw rsd rsd (rs2)
75	74	A64		Xc	store	amo	amo.or.w.aqrl	25	3rsd	3rs2	amo.orw rsd rsd (rs2)
76	75	A64		Xc	store	amo	amo.and.w.aqrl	26	3rsd	3rs2	amo.andw rsd rsd (rs2)
77	76	A64		Xc	store	amo	amo.add.w.aqrl	27	3rsd	3rs3	amo.addw rsd rsd (rs2)
78	77	A		Xc	store	amo	sc.x	20	3rsd	3rs2	sc.wdq rsd rsd (rs2)
79	78	A		Xc	store	amo	sc.x.aq	21	3rsd	3rs2	sc.wdq.aq rsd rsd (rs2)
80	79	A		Xc	store	amo	sc.x.rl	22	3rsd	3rs2	sc.wdq.rl rsd rsd (rs2)
81	80	A		Xc	store	amo	sc.x.aqrl	23	3rsd	3rs2	sc.wdq.aqrl rsd rsd (rs2)
82	81	A64		Xc	store	amo	sc.w	28	3rsd	3rs2	sc.w rsd rsd (rs2)
83	82	A64		Xc	store	amo	sc.w.aq	29	3rsd	3rs2	sc.w.aq rsd rsd (rs2)
84	83	A64		Xc	store	amo	sc.w.rl	30	3rsd	3rs2	sc.w.rl rsd rsd (rs2)
85	84	A64		Xc	store	amo	sc.w.aqrl	31	3rsd	3rs2	sc.w.aqrl rsd rsd (rs2)
86	85
87	86	I	mv	CXc	mv/add	alu	mv	5rd*	5rs2*	0	add rd zero rs2
88	87	I	add	CXc	mv/add	alu	add	5rsd*	5rs2*	1	add rsd rsd rs2
89	88	I	jr	CXc	mv/add	jump	jr	5rs1*	zero	0	jalr zero rs1 0x0 and pop the return stack for odd registers(like ra) donot pop for even registers (or maybe change the immediate to 0x0 or 0x1 depending on the parity of the register)
90	89	I	jalr	CXc	mv/add	jump	jalr_ra	5rs1*	zero	1	jalr ra rs1 0x0	An alternative maybe to have a jalr 5rsd zero --> jalr rsd rsd 0x0. This allows more flexibility than jalr ra 5rs1 and allows to kill jalr 3rd 3rs1
91	90	reserved			mv/add			zero	5rs2*	0
92	91	reserved			mv/add			zero	5rs2*	1
93	92	reserved			mv/add			zero	zero	0
94	93	reserved			mv/add			zero	zero	1
95	94
96	95	I	li	CXc	li	li	li	5rd*	6imm		li rd imm	this inludes setting a register to zero
97	96	reserved			li			zero	6imm			lui_ra ???
98	97
99	98	I		Xc	auipc_ra	li	auipc_ra	11imm			auipc ra imm	intended to be paired with jalr_ra
100	99