HeliumISA.xlsx

	A	B	C	E	G
1	Opcode	short	description	ram:	predicate: executes the next instruction if atleast one condition is true
2	00000---	add	acc = acc + reg	addr. 0: use lower 5 bits of reg 4 as pointer	condititons in order: cout, msb, 0, lsb
3	00001---	sba	acc = acc - reg	addr. 1-31: addr with imm	conditions are inverted
4	00010---	xor	acc = acc ^ reg		pdc needs a delay slot (e.g. add 2, nop, pdc 1011)
5	00011---	and	acc = acc & reg	regs:
6	00100---	lor	acc = acc \| reg	addr. 0,1,2,4,5,6,7: general purpose
7	00101---	sbr	acc = reg - acc	addr. 3: general purpose + ram pointer	load immediate:
8	00110---	inc	acc = acc + 1		the immediate is specified in the next instruction "slot" (e.g. ldi, 123)
9	00111---	dec	acc = acc - 1	io:
10	01000---	ast	reg = acc	addr. 0-15: general io
11	01001---	ald	acc = reg
12	0101----	pgl	load page
13	0110 0000	nop	e
14	0110 0001	hlt	stops the cpu
15	0110 0010	ldi	acc = imm
16	0110 1000	rsh	acc = acc>>1
17	0111----	pdc	predicate
18	100-----	ral	acc = ram
19	101-----	ras	ram = acc
20	110-----	jmp	pc = imm
21	1110----	out	port = acc await
22	1111----	inp	acc = port await
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