DDR5 Timing Calculator for AMD

	A	B	C	D	E	F	G	H	I
1	DDR5 Timing Calculator for AMD by RedF & Wolf87, Guided by Veii
2									Version 0.0.05
3	Primary Timings	use this formula at your own risk				calculated	Edit	do not touch !
4	tCL	30
5	tRCDWR	36
6	tRCDRD	36
7	tRP	36
8	tRTP	12
9	tWR	48
10
11	minimum tRAS	48	tRCD	tRTP
12	tRCD+tRTP	48	36	12
13
14	optimum tRAS	58	tRCD	tRTP	BurstLength 16 / 2 = BurstChop	X = + 2 or 4 Points, minimum = 0
15	tRCD + tRTP + BurstChop + X	58	36	12	8	2
16
17	safe tRAS		tCWL	tRCDWR	tWR	Diese Variante garantiert laut Veii immer einen ROW Hit
18	tCWL+tRCDWR+WR	112	28	36	48
19	tRC = tRAS, for safe tRAS	112	28	36	48
20
21	tRC = for tRAS minimum or optimum	tRC = for tRAS min	tRC = for tRAS Optimum
22	tRC = for tRAS minimum or optimum	84	94
23
24	tFAW	32	User Veii: Für alle unsere DIMMs ~ 32. 32 für 1kb pagesize dimms 48 für 2kb pagesize dimms. // Solange nicht bestätigt wird dass AMD 2 MC links pro DIMM nützt, ist es Wert 32/48 anstelle 16/24 :)
25									User Veii: RFC if you stay with 65535 maxed, is 320,352,384,416 If you want to give 65528 a try , then its 308, 340, 372 ,404 ~ pick one that suits you Scale both sets +/- 32. But keep values. Just test what REFI brings you most consistency(not latency)
26	tRFC	choose your value	Hynix A-Die [ns]	Hynix M-Die [ns]	Samsung B-Die [ns]	Samsung D-Die [ns]	Micron A+G REV [ns]	Micron Rev B [ns]
27	choose your clock value and your tRFC for your Dimm type		120	160	260	270	260	360
28	DDR5 MHz	8000							choose your clock value
29	tRFC [tREFi 65528]	628	157,0	157,0	157,0	157,0	157,0	157,0	if you use tREFi 65528, red value=if you reach min Value
30	tRFC [tREFi 65535]	704	176,0	176,0	176,0	176,0	176,0	176,0	if you use tREFi 65535, red value=if you reach min Value
31
32	Transition Timings
33	tRRD_S/DG	8
34	tRRD_L/SG	12	recommended 12
35	tWTR_S/DG	7
36	tWTR_L/SG	24
38
39	Interface Timings
40	CCD_S		8
41	CCD_L	=>tRRDL oder tRRDS	12
42	CCDL_WR	= CCDL *2	24
43
44	Mathematical Offset Timings
45	tRDRDSC_L min	5	CCDL	RdBurstChop	OdtEnDly
46	CCDL - RdBurstChop + ODTEnDly	5	12	8	1
47
48	tWRWRSC_L min	17	CCDLWR	WrBurstChop	OdtEnDly
49	CCDLWR - WrBurstChop + ODTEnDly	17	24	8	1
50
51	tRDWR min	14	tCL	tCWL	BurstChop	OdtEnDly	WrPRE 2-4 / über MemTweakIT auslesbar	safety delay
52	tCL - tCWL + BC8 + ODTEnDly + WrPRE + SafetyDly	14	30	28	8	1	2	1
53
54	_DD & _SD/DR	JEDEC Specs	wenn 2x32bit MC/DIMM
55	tCCD_S	8	4
56	tRDRD_	8	4
57	tWRWR_	6	3
58	tRDWR_	16	8	Vorerst nicht auf Ryzen zu finden. Eventuell auf EPYC
59	tWRRD_	4	2	Vorerst nicht auf Ryzen zu finden. Eventuell auf EPYC
60
61	tREFi < Maximum Wert 65536(-1), bitte Wert aus Spalte auswählen	57343	65536 (minus 8192 steps) = resultat -1. // to choose for thermal problems
62
63	tRRD_L/SG	16GB Dimm	24GB Dimm
64	tCCD_S oder höher	8	12	.= CCDS , or bigger. CCDS is always 8 unless double MC link. Starting point 8+
65
66	Refresh Timings	tRFC
67	tRFC	640
68	tRFC2	347
69	tRFCsb	282
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