X65 memory map

	B	C	D	E	F	G
1	FFFF	IRQB/BRK	CPU	6502 vector.
2	FFFE	IRQB/BRK	CPU	6502 vector.		Legend:
3	FFFD	RESETB	CPU	6502 vector.		Not implemented yet
4	FFFC	RESETB	CPU	6502 vector.		Implemented in Emu only
5	FFFB	NMIB	CPU	6502 vector.
6	FFFA	NMIB	CPU	6502 vector.
7	FFF9	ABORTB	CPU	65816 vector.
8	FFF8	ABORTB	CPU	65816 vector.
9	FFF7	EXTMEM	HW	Reserved for future use (extended memory MMU)
10	FFF6	EXTIOCTL	HW	Bitmap of 8x 64byte chunks for mapping RAM into I/O area.	Maps $FC00-$FDFF to extension devices.	Two last pages of bank 0 (`$00FE00` - `$00FFFF`) is dedicated to internal I/O devices.
11	FFF5	COP	CPU	65816 vector.		Area $FC00-$FDFF is used to handle extension devices. Divided into 4x 128byte chunks. If you _really_ need to use RAM in this area, use `$00FFF6` register to map RAM chunks in.
12	FFF4	COP	CPU	65816 vector.
13	FFF3	STATUS	API	Bit 7 high while operation is running.	Bit 0 high when ERRNO.
14	FFF2	STACK	API	512 bytes for passing call parameters.
15	FFF1	RET_HI	API	High byte of 16 bit return value. Otherwise `0`.	API error number. 16 bit.
16	FFF0	OP / RET	API	Write the API operation id here to begin a kernel call. Read return value.	API error number. 16 bit.
17	FFEF	IRQB	CPU	65816 vector.		Interrupt Sources:
18	FFEE	IRQB	CPU	65816 vector.		0 - RIA
19	FFED	IRQ_STATUS	INT	Interrupt Controller	Read to get IRQ interrupt state	1 - GPIO extender
20	FFEC	IRQ_ENABLE	RIA	RIA interrupts enable	Enable RIA interrupts	2 - unused
21	FFEB	NMIB	CPU	65816 vector.		3 - I2C port
22	FFEA	NMIB	CPU	65816 vector.		4-7 - Extended I/O
23	FFE9	ABORTB	CPU	65816 vector.
24	FFE8	ABORTB	CPU	65816 vector.		RIA Interrupts:
25	FFE7	BRK	CPU	65816 vector.		0 - CIA-compatible timers
26	FFE6	BRK	CPU	65816 vector.		1-7 - reserved
27	FFE5	COP	CPU	65816 vector.
28	FFE4	COP	CPU	65816 vector.
29	FFE3	RNG	HW	Random Number Generator
30	FFE2	RNG	HW	Random Number Generator
31	FFE1	TX, RX	UART	Write bytes to the UART.	Read bytes from the UART.
32	FFE0	READY	UART	Flow control for UART FIFO.	bit 7 - TX FIFO not full. Ok to send. bit 6 - RX FIFO has data ready.
33	FFDF	FDBST	FS	File-descriptor B status.
34	FFDE	FDAST	FS	File-descriptor A status.	bit 7 - open; bit 6 - EOF; bit 1 - writable; bit 0 - readable (data waiting)
35	FFDD	FDBRW	FS	Read bytes from the FDB. Write bytes to the FDB.
36	FFDC	FDARW	FS	Read bytes from the FDA. Write bytes to the FDA.
37	FFDB	FDB	FS	File-descriptor B number.
38	FFDA	FDA	FS	File-descriptor A number. (Obtained from open() API call.)
39	FFD9	DMAERR	DMA	DMA transfer errno.
40	FFD8	COUNT	DMA	DMA transfers count.	write - start the DMA transfer. read - non-zero when transfer is in-progress.
41	FFD7	STEPDST	DMA	DMA destination step.
42	FFD6	ADDRDST	DMA	DMA destination address.
43	FFD5
44	FFD4
45	FFD3	STEPSRC	DMA	DMA source step.
46	FFD2	ADDRSRC	DMA	DMA source address.
47	FFD1
48	FFD0
49	FFCF	TM5	TIME	Time Of Day (µs)
50	FFCE	TM4
51	FFCD	TM3
52	FFCC	TM2
53	FFCB	TM1
54	FFCA	TM0
55	FFC9	DIVAB	MATH	Signed OPERA / unsigned OPERB.
56	FFC8	DIVAB	MATH	Signed OPERA / unsigned OPERB.
57	FFC7	MULAB	MATH	OPERA * OPERB.
58	FFC6
59	FFC5
60	FFC4
61	FFC3	OPERB	MATH	Operand B for multiplication and division.
62	FFC2	OPERB	MATH	Operand B for multiplication and division.
63	FFC1	OPERA	MATH	Operand A for multiplication and division.
64	FFC0	OPERA	MATH	Operand A for multiplication and division.		RIA816 registers ($40 registers) end here
65	FFBF	HID_D15	HID	Device dependant data		RIA816 hardware proxy area ($40 registers) follows
66	FFBE	HID_D14	HID
67	FFBD	HID_D13	HID
68	FFBC	HID_D12	HID
69	FFBB	HID_D11	HID
70	FFBA	HID_D10	HID
71	FFB9	HID_D9	HID
72	FFB8	HID_D8	HID
73	FFB7	HID_D7	HID
74	FFB6	HID_D6	HID		D evice type:
75	FFB5	HID_D5	HID		0 - kbd (all merged, AAAA selects 16-key block)
76	FFB4	HID_D4	HID		1 - mou (all merged)
77	FFB3	HID_D3	HID		2 - pad (0th merged, AAAA nth - selectable)
78	FFB2	HID_D2	HID
79	FFB1	HID_D1	HID
80	FFB0	HID_D0/SELECT	HID		Write: [ AAAA DDDD ] - D - device type, A - device address/index
81	FFAF
82	FFAE
83	FFAD
84	FFAC
85	FFAB	BUZZ_RES	BUZZER		The FREQ register is a 16-bit logarithmic pitch value, not a linear Hz/divider. We map the full 0..65535 range onto ~20 Hz..20 kHz by making FREQ linear in log2(f). FREQ_16 = round( 65535 * log2(f_hz / 20) / log2(20000 / 20) )	Buzzer is handled in south-bridge
86	FFAA	BUZZ_DUTY	BUZZER	BUZZER duty cycle 0..255 (0%..100%) ; 0 mutes BUZZER
87	FFA9	BUZZ_FREQ_HI	BUZZER	BUZZER frequency (16 bit) low and high byte
88	FFA8	BUZZ_FREQ_LO	BUZZER	BUZZER frequency (16 bit) low and high byte
89	FFA7	LED_BLUE	RGB	A chain of WS2812B directly addressable RGB LEDs.	BLUE value for Indexed set
90	FFA6	LED_GREEN	RGB		GREEN value for Indexed set
91	FFA5	LED_RED	RGB		RED value for Indexed set
92	FFA4	LED_IDX	RGB		LED Index - write to set the LED with RED,GREEN,BLUE
93	FFA3	LED3	RGB		Direct set LED 3
94	FFA2	LED2	RGB		Direct set LED 2
95	FFA1	LED1	RGB		Direct set LED 1
96	FFA0	LED0	RGB		Direct set LED 0 (with RGB332 color)
97	FF9F	CRB_0F	TIMERS	CIA-compatible timers Running @ 1MHz tick	CONTROL REG B
98	FF9E	CRA_0E	TIMERS		CONTROL REG A
99	FF9D	ICR_0D	TIMERS		INTERRUPT CONTROL REGISTER
100	FF9C				??? frequency control ???