PCI Express Development Board Pin Mapping

	A	B	C	D	F	G	I	J	K	L
1		PCI Express Usage			PCI Express Mapping on Spartan 6		Xilinx Kintex-7 FPGA KC705 Evaluation Kit
2	Pin	Side B	Side A	Description	PCI Express Mapping on Spartan 6		FPGA Pin		Net Name

3							PCIe Standard		PCIe x8 Gen 2	5 GT/s, 100MHz Clk
4							Board Features		Kintex-7 (XC7K325T-2FFG900C), 1GB DDR3, PCIe - 4x, FMC-HPC, FMC-LPC
5							GTP Features		7 Series FPGAs
6
7	1	+12 V	PRSNT1#	Must connect to farthest PRSNT2# pin	+12 V	PRSNT1#	NC	J32 2/4/6	NC	N/A
8	2	+12 V	+12 V		+12 V	+12 V	NC	NC	NC	NC
9	3	+12 V	+12 V		+12 V	+12 V	NC	NC	NC	NC
10	4	GND	GND		GND	GND	NC	NC	NC	NC
11	5	SMCLK	TCK	SMBus and JTAG port pins	SMCLK	TCK	NC	NC	NC	NC
12	6	SMDAT	TDI		SMDAT	TDI	NC	NC	NC	NC
13	7	GND	TDO		GND	TDO	NC	NC	NC	NC
14	8	+3.3 V	TMS		+3.3 V	TMS	NC	NC	NC	NC
15	9	TRST#	+3.3 V		TRST#	+3.3 V	NC	NC	NC	NC
16	10	+3.3 V aux	+3.3 V	Standby power	+3.3 V aux	+3.3 V	NC	NC	NC	NC
17	11	WAKE#	PERST#	Link reactivation; fundamental reset	WAKE#	PERST#	F23	G25	N/A	N/A
18	11.5	Key notch			Key notch		NC	NC	NC	NC
19	12	CLKREQ#	GND	Request running clock	CLKREQ#	GND	NC	NC	NC	NC
20	13	GND	REFCLK+	Reference clock differential pair	GND	PCIE_CLK_Q0_P	NC	U8	NC	MGT_BANK_115
21	14	HSOp(0)	REFCLK−	Lane 0 transmit data, + and −	PCIE_RX0_P	PCIE_CLK_Q0_N	M6	U7	GTXE2_CHANNEL_X0Y7	MGT_BANK_115
22	15	HSOn(0)	GND	Lane 0 transmit data, + and −	PCIE_RX0_N	GND	M5	NC	GTXE2_CHANNEL_X0Y7	NC
23	16	GND	HSIp(0)	Lane 0 receive data, + and −	GND	PCIE_TX1_P	NC	L4	NC	GTXE2_CHANNEL_X0Y7
24	17	PRSNT2#	HSIn(0)	Lane 0 receive data, + and −	PRSNT2#	PCIE_TX1_N	NC	L3	NC	GTXE2_CHANNEL_X0Y7
25	18	GND	GND		GND	GND	NC	NC	NC	NC
26	18.5	PCI Express ×1 cards end at pin 18			PCI Express ×1 cards end at pin 18		NC	NC	NC	NC
27	19	HSOp(1)	Reserved	Lane 1 transmit data, + and −	PCIE_RX2_P	NC	P6	NC	GTXE2_CHANNEL_X0Y6	NC
28	20	HSOn(1)	GND	Lane 1 transmit data, + and −	PCIE_RX2_N	GND	P5	NC	GTXE2_CHANNEL_X0Y6	NC
29	21	GND	HSIp(1)	Lane 1 receive data, + and −	GND	PCIE_TX2_P	NC	M2	NC	GTXE2_CHANNEL_X0Y6
30	22	GND	HSIn(1)	Lane 1 receive data, + and −	GND	PCIE_TX2_N	NC	M1	NC	GTXE2_CHANNEL_X0Y6
31	23	HSOp(2)	GND	Lane 2 transmit data, + and −	PCIE_RX3_P	GND	R4	NC	GTXE2_CHANNEL_X0Y5	NC
32	24	HSOn(2)	GND	Lane 2 transmit data, + and −	PCIE_RX3_N	GND	R3	NC	GTXE2_CHANNEL_X0Y5	NC
33	25	GND	HSIp(2)	Lane 2 receive data, + and −	GND	PCIE_TX3_P	NC	N4	NC	GTXE2_CHANNEL_X0Y5
34	26	GND	HSIn(2)	Lane 2 receive data, + and −	GND	PCIE_TX3_N	NC	N3	NC	GTXE2_CHANNEL_X0Y5
35	27	HSOp(3)	GND	Lane 3 transmit data, + and −	PCIE_RX4_P	GND	T6	NC	GTXE2_CHANNEL_X0Y4	NC
36	28	HSOn(3)	GND	Lane 3 transmit data, + and −	PCIE_RX4_N	GND	T5	NC	GTXE2_CHANNEL_X0Y4	NC
37	29	GND	HSIp(3)	Lane 3 receive data, + and −	GND	PCIE_TX4_P	NC	P2	NC	GTXE2_CHANNEL_X0Y4
38	30	Reserved	HSIn(3)	Lane 3 receive data, + and −	NC	PCIE_TX4_N	NC	P1	NC	GTXE2_CHANNEL_X0Y4
39	31	PRSNT2#	GND		PRSNT2#	GND	NC	NC	NC	NC
40	32	GND	Reserved		GND	NC	NC	NC	NC	NC
41	32.5	PCI Express ×4 cards end at pin 32			PCI Express ×4 cards end at pin 32		NC	NC	NC	NC
42	33	HSOp(4)	Reserved	Lane 4 transmit data, + and −			V6	NC	GTXE2_CHANNEL_X0Y3	NC
43	34	HSOn(4)	GND	Lane 4 transmit data, + and −			V5	NC	GTXE2_CHANNEL_X0Y3	NC
44	35	GND	HSIp(4)	Lane 4 receive data, + and −			NC	T2	NC	GTXE2_CHANNEL_X0Y3
45	36	GND	HSIn(4)	Lane 4 receive data, + and −			NC	T1	NC	GTXE2_CHANNEL_X0Y3
46	37	HSOp(5)	GND	Lane 5 transmit data, + and −			W4	NC	GTXE2_CHANNEL_X0Y2	NC
47	38	HSOn(5)	GND	Lane 5 transmit data, + and −			W3	NC	GTXE2_CHANNEL_X0Y2	NC
48	39	GND	HSIp(5)	Lane 5 receive data, + and −			NC	U4	NC	GTXE2_CHANNEL_X0Y2
49	40	GND	HSIn(5)	Lane 5 receive data, + and −			NC	U3	NC	GTXE2_CHANNEL_X0Y2
50	41	HSOp(6)	GND	Lane 6 transmit data, + and −			Y6	NC	GTXE2_CHANNEL_X0Y1	NC
51	42	HSOn(6)	GND	Lane 6 transmit data, + and −			Y5	NC	GTXE2_CHANNEL_X0Y1	NC
52	43	GND	HSIp(6)	Lane 6 receive data, + and −			NC	V2	NC	GTXE2_CHANNEL_X0Y1
53	44	GND	HSIn(6)	Lane 6 receive data, + and −			NC	V1	NC	GTXE2_CHANNEL_X0Y1
54	45	HSOp(7)	GND	Lane 7 transmit data, + and −			AA4	NC	GTXE2_CHANNEL_X0Y0	NC
55	46	HSOn(7)	GND	Lane 7 transmit data, + and −			AA3	NC	GTXE2_CHANNEL_X0Y0	NC
56	47	GND	HSIp(7)	Lane 7 receive data, + and −			NC	Y2	NC	GTXE2_CHANNEL_X0Y0
57	48	PRSNT2#	HSIn(7)	Lane 7 receive data, + and −			NC	Y1	NC	GTXE2_CHANNEL_X0Y0
58	49	GND	GND				NC	NC	NC	NC
59	49.5	PCI Express ×8 cards end at pin 49					Board ends here
60	50	HSOp(8)	Reserved	Lane 8 transmit data, + and −
61	51	HSOn(8)	GND	Lane 8 transmit data, + and −
62	52	GND	HSIp(8)	Lane 8 receive data, + and −
63	53	GND	HSIn(8)	Lane 8 receive data, + and −
64	54	HSOp(9)	GND	Lane 9 transmit data, + and −
65	55	HSOn(9)	GND	Lane 9 transmit data, + and −
66	56	GND	HSIp(9)	Lane 9 receive data, + and −
67	57	GND	HSIn(9)	Lane 9 receive data, + and −
68	58	HSOp(10)	GND	Lane 10 transmit data, + and −
69	59	HSOn(10)	GND	Lane 10 transmit data, + and −
70	60	GND	HSIp(10)	Lane 10 receive data, + and −
71	61	GND	HSIn(10)	Lane 10 receive data, + and −
72	62	HSOp(11)	GND	Lane 11 transmit data, + and −
73	63	HSOn(11)	GND	Lane 11 transmit data, + and −
74	64	GND	HSIp(11)	Lane 11 receive data, + and −
75	65	GND	HSIn(11)	Lane 11 receive data, + and −
76	66	HSOp(12)	GND	Lane 12 transmit data, + and −
77	67	HSOn(12)	GND	Lane 12 transmit data, + and −
78	68	GND	HSIp(12)	Lane 12 receive data, + and −
79	69	GND	HSIn(12)	Lane 12 receive data, + and −
80	70	HSOp(13)	GND	Lane 13 transmit data, + and −
81	71	HSOn(13)	GND	Lane 13 transmit data, + and −
82	72	GND	HSIp(13)	Lane 13 receive data, + and −
83	73	GND	HSIn(13)	Lane 13 receive data, + and −
84	74	HSOp(14)	GND	Lane 14 transmit data, + and −
85	75	HSOn(14)	GND	Lane 14 transmit data, + and −
86	76	GND	HSIp(14)	Lane 14 receive data, + and −
87	77	GND	HSIn(14)	Lane 14 receive data, + and −
88	78	HSOp(15)	GND	Lane 15 transmit data, + and −
89	79	HSOn(15)	GND	Lane 15 transmit data, + and −
90	80	GND	HSIp(15)	Lane 15 receive data, + and −
91	81	PRSNT2#	HSIn(15)	Lane 15 receive data, + and −
92	82	Reserved	GND
93		PCI Express ×16 cards end at pin 82
94	Color	Legend		Legend
95		GND pin		Zero volt reference
96		Power pin		Supplies power to the PCIe card
97		Output pin		Signal from the card to the motherboard
98		Input pin		Signal from the motherboard to the card
99		Open drain		May be pulled low or sensed by multiple cards
100		Sense pin		Tied together on card