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DC-SCI Pin Definition 
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The DC-SCI connector pinout includes the single name (preferred board net name that include functional and directional nomenclature), gold finger lengths, single node usages, voltage, direction, typical usages and dual node usage.
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The contact sequence for each pin indicates the order in which the pins make contact between the HPM and the DC-SCM. The GND pins are required to be long pins or 1st mate. The PRSNT0_N/ PRSNT1_N pins and P12V_AUX pins are required to be short pins or 2nd mate. However, the remaining pins indicated as 2nd mate can be flexibly assigned as long pins/1st mate if dictated by design or DFM requirements.
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Multi-function DC-SCI pins list the functions in order starting with the most typical expected usage.
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When multiple voltages are listed for a signal, they map the respective alternate pin function order.
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DC-SCI Signal Descriptions 
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The following sections provide the signal descriptions of signals through the DC-SCI. 
The signal names are constructed using the notation of:
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 function_(bus source)_(signal source)_(signal destination)_Instance#_Node#_Polarity  
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 Node 1 omits the Node #. Functions with only 1 instance do not include 0. Polarity of active low uses the *_N naming.
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Note: Follow device datasheet recommendations to appropriately terminate un-used signals on the DC-SCM. 
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Abbreviation Definition: 
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Symbol Description
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_N or #  Denotes active low signal
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Input  Input to DC-SCM
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Output  Output from DC-SCM
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InOut At least one of the functions is a bidirectional signal
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CHANGES MADE
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10/12/2021 0.95g Removed voltages from LTPI and PCIe since they aren't DC 1.8V.; Fixed missing A69 clock name; Clarified USB2.0 power domains for each of the exclusive modes/directions); Addded some dual node stats
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10/25/2021 0.95h Updated I2C_I3C naming and bus numbering; Swapped UART1 RX and TX to better align with the direction of the 2 alt functions
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11/9/2021 0.95i Removed HPM_SCM on UART0 and UART1 4 pins since link partners are peers and not a controller / target relationship. Making signal names more generic.
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11/9/2021 0.95j Added UART directions in the direction column AND swapped UART0 and UART1 RX and TX to match the direction of the other functions on those 2 pins.
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11/18/2021 0.95kFixed truncated name to: UART1_TX, removing HPM_SCM since either direction is supported
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11/19/2021 0.95lChanged the alternative function order for SPI_HPMCNTRL_TPM_CS_N to match I2C_I3C_1V8_10 signals as first alternative.
Changed the name of SPI_SCMCNTRL_IRQ0_N to indicate the IRQ0 is related to immutable SPI terface.
Changed the names of LVDS to LTPI and fixed the naming convention to SRC_DST approach.
Changed the UART0/1 names to follow SRC_DST naming convention.
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1/10/2022 0.95mAdded alt functions of SGMII, USB3 and LTPI2 on PCIe X4
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1/19/2022 0.95nAdded alt functions of USB3 and LTPI2 on PCIe X4 for Dual node with updated power states definitions. SGMII is not added for dual node due to high number of alt-functions.
bug fix: removed _1 for I2C_19
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3/28/2022 0.95o Remove LTPI_DATA2 and 3 - not necessary or requested by anyone.
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Fixed USB3_SCMROOT to USB3_SCMHOST for proper nomenclature
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Change name B36-37 from USB2_SCMHOST_DN to USB2_SCMHOST1_DN. Same for dual node
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Change name B68-69 from USB2_BMC_SCMOTG to USB2_SCMHOST2. Same for dual node
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Add USB2_SCMROOT3 to OB11-OB12
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Add DisplayPort (2 lane output + AUX channel diff pair) to OA5-OB6 and OA11-OA12. Note DP's hotplug detect would be a serialized GPIO back to BMC
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Remove GPIO 3rd pin function option from B36-B37 and B68-B69; Rationale: USB interfaces seem likely to be needed near 100% of the time
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Added SGPIO on B52-B55 for peer node communication, simple remote subsystem virtual wires or other early boot sequence usages
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Remove GPO from B51 - already 3 other functions.
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Added the direction for each function on a pin (general).
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Changed NCSI alt functions from GPI and GPO to GPIO
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Clarified I2C3-6/ dual node eSPI as 3.3V in single and 1.8V in dual mode respectively
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Added SGPIO / GPIO in Dual Node and BMC PERST
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4/4/2022 0.98snap shot for review
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5/6/2022 0.99B33/B34 Dual node add USB3_SCMHOST1_HPM_SCM_DN/DP
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updated interface count table
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6/1/2022Add GPO back to B51
Add GPIO back to B36, B37, B68, B69
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6/24/2022match S68 pin name with M68
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7/27/2022 1.0ver 1.0 release
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