vHW CPU flags
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vmx-7vmx-8vmx-9vmx-10vmx-11vmx-13vmx-14descsince
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fpufpufpufpufpufpufpuOnboard FPU (floating point support)
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vmevmevmevmevmevmevmeVirtual 8086 mode enhancements
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dededededededeDebugging Extensions (CR4.DE)
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psepsepsepsepsepsepsePage Size Extensions (4MB memory pages)
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tsctsctsctsctsctsctscTime Stamp Counter (RDTSC)
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msrmsrmsrmsrmsrmsrmsrModel-Specific Registers (RDMSR, WRMSR)
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paepaepaepaepaepaepaePhysical Address Extensions (support for more than 4GB of RAM)
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mcemcemcemcemcemcemceMachine Check Exception
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cx8cx8cx8cx8cx8cx8cx8CMPXCHG8 instruction (64-bit compare-and-swap)
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apicapicapicapicapicapicapicOnboard APIC
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sepsepsepsepsepsepsepSYSENTER/SYSEXIT
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mtrrmtrrmtrrmtrrmtrrmtrrmtrrMemory Type Range Registers
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pgepgepgepgepgepgepgePage Global Enable (global bit in PDEs and PTEs)
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mcamcamcamcamcamcamcaMachine Check Architecture
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cmovcmovcmovcmovcmovcmovcmovCMOV instructions (conditional move) (also FCMOV)
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patpatpatpatpatpatpatPage Attribute Table
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pse36pse36pse36pse36pse36pse36pse3636-bit PSEs (huge pages)
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clflushclflushclflushclflushclflushclflushclflushCache Line Flush instruction
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dtsdtsdtsdtsdtsdtsdtsDebug Store (buffer for debugging and profiling instructions)
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mmxmmxmmxmmxmmxmmxmmxMultimedia Extensions
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fxsrfxsrfxsrfxsrfxsrfxsrfxsrFXSAVE/FXRSTOR, CR4.OSFXSR
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ssessessessessessesseIntel SSE vector instructions
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sse2sse2sse2sse2sse2sse2sse2SSE2
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ssssssssssssssCPU self snoop
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hththththththtHyper-Threading
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syscallsyscallsyscallsyscallsyscallsyscallsyscallSYSCALL (Fast System Call) and SYSRET (Return From Fast System Call)
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nxnxnxnxnxnxnxExecute Disable
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pdpe1gbpdpe1gbpdpe1gbpdpe1gbpdpe1gbOne GB pages (allows hugepagesz=1G)Westmere
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rdtscprdtscprdtscprdtscprdtscprdtscprdtscpRead Time-Stamp Counter and Processor ID
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lmlmlmlmlmlmlmLong Mode (x86-64: amd64, also known as Intel 64, i.e. 64-bit capable)
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constant_tscconstant_tscconstant_tscconstant_tscconstant_tscconstant_tscconstant_tscTSC ticks at a constant rate
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arch_perfmon
arch_perfmon
arch_perfmonarch_perfmonarch_perfmonarch_perfmonarch_perfmonIntel Architectural PerfMon
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pebspebspebspebspebspebspebsPrecise-Event Based Sampling
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btsbtsbtsbtsbtsbtsbtsBranch Trace Store
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noplnoplnoplnoplnoplnoplnoplThe NOPL (0F 1F) instructions
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xtopologyxtopologyxtopologyxtopologyxtopologyxtopologyxtopologyCPU topology enum extensionsNahalem
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tsc_reliabletsc_reliabletsc_reliabletsc_reliabletsc_reliabletsc_reliabletsc_reliableTSC is known to be reliable
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nonstop_tscnonstop_tscnonstop_tscnonstop_tscnonstop_tscnonstop_tscnonstop_tscTSC does not stop in C states
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eagerfpueagerfpueagerfpueagerfpueagerfpueagerfpueagerfpuNon lazy FPU restore
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pnipnipnipnipnipnipniSSE-3 (“Prescott New Instructions”)
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pclmulqdqpclmulqdqpclmulqdqpclmulqdqpclmulqdqpclmulqdqpclmulqdq
Perform a Carry-Less Multiplication of Quadword instruction — accelerator for GCM)
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ssse3ssse3ssse3ssse3ssse3ssse3ssse3Supplemental SSE-3
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fmafmafmafmafmafmaFused multiply-addHaswell
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cx16cx16cx16cx16cx16cx16cx16CMPXCHG16B
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pcidpcidpcidpcidpcidProcess Context IdentifiersWestmere
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sse4_1sse4_1sse4_1sse4_1sse4_1sse4_1sse4_1SSE-4.1
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sse4_2sse4_2sse4_2sse4_2sse4_2sse4_2sse4_2SSE-4.2
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x2apicx2apicx2apicx2apicx2apicx2APICNahalem
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movbemovbemovbemovbemovbemovbemovbeMove Data After Swapping Bytes instructionHaswell
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popcntpopcntpopcntpopcntpopcntpopcntpopcnt
Return the Count of Number of Bits Set to 1 instruction (Hamming weight, i.e. bit count)
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tsc_deadline_timer
tsc_deadline_timer
tsc_deadline_timer
TSC deadline timerWestmere
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aesaesaesaesaesaesaesAdvanced Encryption Standard (New Instructions)
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xsavexsavexsavexsavexsavexsaveSave Processor Extended States: also provides XGETBY,XRSTOR,XSETBYSandy Bridge
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avxavxavxavxavxavxAdvanced Vector ExtensionsSandy Bridge
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f16cf16cf16cf16cf16c16-bit fp conversions (CVT16)Ivy Bridge
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rdrandrdrandrdrandrdrandrdrand
Read Random Number from hardware random number generator instruction
Ivy Bridge
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hypervisorhypervisorhypervisorhypervisorhypervisorhypervisorhypervisorRunning on a hypervisor
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lahf_lmlahf_lmlahf_lmlahf_lmlahf_lmlahf_lmlahf_lmLoad AH from Flags (LAHF) and Store AH into Flags (SAHF) in long modeNahalem
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abmabmabmAdvanced bit manipulationHaswell
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3dnowprefetch
3dnowprefetch
3dnowprefetch3dnowprefetch3dnowprefetch3dnowprefetch3dnowprefetch3DNow prefetch instructions
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ssbdssbdssbdssbdssbdSpeculative Store Bypass Disable (SSBD)
CVE-2017-5715
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ibrsibrsibrsibrsibrsIndirect Branch Restricted Speculation
CVE-2017-5715
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ibpbibpbibpbibpbibpbIndirect Branch Prediction Barrier
CVE-2017-5715
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stibpstibpstibpstibpstibpSingle Thread Indirect Branch Predictors
CVE-2017-5715
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fsgsbasefsgsbasefsgsbasefsgsbasefsgsbase{RD/WR}{FS/GS}BASE instructionsIvy Bridge
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tsc_adjusttsc_adjusttsc_adjustTSC adjustment MSR 0x3BIvy Bridge
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bmi1bmi1bmi11st group bit manipulation extensionsHaswell
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hlehlehleHardware Lock ElisionHaswell
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avx2avx2avx2AVX2 instructionsHaswell
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smepsmepsmepsmepsmepSupervisor Mode Execution ProtectionIvy Bridge
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bmi2bmi2bmi22nd group bit manipulation extensionsHaswell
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invpcidinvpcidinvpcidInvalidate Processor Context IDHaswell
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rtmrtmrtmRestricted Transactional MemoryHaswell
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mpxmpxMemory Protection ExtensionSkylake
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rdseedrdseedrdseedThe RDSEED instructionBroadwell
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adxadxadxThe ADCX and ADOX instructionsBroadwell
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smapsmapsmapSupervisor Mode Access PreventionBroadwell
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clflushoptclflushoptCLFLUSHOPT instructionSkylake
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xsaveoptxsaveoptxsaveoptXSAVEOPT instructionSandy Bridge
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xsavecxsavecXSAVEC instructionSkylake
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aratarataratarataratarataratAlways Running APIC Timer
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md_clearmd_clearmd_clearmd_clearmd_clearVERW clears CPU buffers
CVE-2019-11091
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spec_ctrlspec_ctrlspec_ctrlspec_ctrlspec_ctrlSpeculation Control (IBRS + IBPB)
CVE-2017-5715
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intel_stibpintel_stibpintel_stibpintel_stibpintel_stibpSingle Thread Indirect Branch Predictors
CVE-2017-5715
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flush_l1dflush_l1dflush_l1dflush_l1dflush_l1dFlush L1D cache
CVE-2018-3646
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arch_capabilities
arch_capabilities
arch_capabilitiesarch_capabilitiesarch_capabilitiesIA32_ARCH_CAPABILITIES MSR (Intel)
CVE-2017-5715
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