| A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | ||
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1 | MAKE A COPY OF THIS SHEET | Instruction Metadata | ROM Input | Control Signals | ROM Output | ||||||||||||||
2 | addi is provided as an example | ||||||||||||||||||
3 | Instruction | Type | Opcode | Funct3 | Funct7 | Binary | Decimal | RegWEn | ImmSel | BrUn | ASel | BSel | ALUSel | MemRW | WBSel | CSRSel | CSRWen | Hex | |
4 | 1 binary digit | 3 binary digits | 1 binary digit | 1 binary digit | 1 binary digit | 4 binary digits | 1 binary digit | 2 binary digits | 1 binary digit | 1 binary digit | |||||||||
5 | add rd, rs1, rs2 | R | 0b0110011 | 0b000 | 0b0000000 | 0b000000 | 0 | 0000 | |||||||||||
6 | mul rd, rs1, rs2 | 0b000 | 0b0000001 | 0b000001 | 1 | 0000 | |||||||||||||
7 | sub rd, rs1, rs2 | 0b000 | 0b0100000 | 0b000010 | 2 | 0000 | |||||||||||||
8 | sll rd, rs1, rs2 | 0b001 | 0b0000000 | 0b000011 | 3 | 0000 | |||||||||||||
9 | mulh rd, rs1, rs2 | 0b001 | 0b0000001 | 0b000100 | 4 | 0000 | |||||||||||||
10 | mulhu rd, rs1, rs2 | 0b011 | 0b0000001 | 0b000101 | 5 | 0000 | |||||||||||||
11 | slt rd, rs1, rs2 | 0b010 | 0b0000000 | 0b000110 | 6 | 0000 | |||||||||||||
12 | xor rd, rs1, rs2 | 0b100 | 0b0000000 | 0b000111 | 7 | 0000 | |||||||||||||
13 | srl rd, rs1, rs2 | 0b101 | 0b0000000 | 0b001000 | 8 | 0000 | |||||||||||||
14 | sra rd, rs1, rs2 | 0b101 | 0b0100000 | 0b001001 | 9 | 0000 | |||||||||||||
15 | or rd, rs1, rs2 | 0b110 | 0b0000000 | 0b001010 | 10 | 0000 | |||||||||||||
16 | and rd, rs1, rs2 | 0b111 | 0b0000000 | 0b001011 | 11 | 0000 | |||||||||||||
17 | lb rd, offset(rs1) | I | 0b0000011 | 0b000 | 0b001100 | 12 | 0000 | ||||||||||||
18 | lh rd, offset(rs1) | 0b001 | 0b001101 | 13 | 0000 | ||||||||||||||
19 | lw rd, offset(rs1) | 0b010 | 0b001110 | 14 | 0000 | ||||||||||||||
20 | addi rd, rs1, imm | 0b0010011 | 0b000 | 0b001111 | 15 | 1 | 001 | 0 | 0 | 1 | 0000 | 0 | 01 | 0 | 0 | 9204 | |||
21 | slli rd, rs1, imm | 0b001 | 0b0000000 | 0b010000 | 16 | 0000 | |||||||||||||
22 | slti rd, rs1, imm | 0b010 | 0b010001 | 17 | 0000 | ||||||||||||||
23 | xori rd, rs1, imm | 0b100 | 0b010010 | 18 | 0000 | ||||||||||||||
24 | srli rd, rs1, imm | 0b101 | 0b0000000 | 0b010011 | 19 | 0000 | |||||||||||||
25 | srai rd, rs1, imm | 0b101 | 0b0100000 | 0b010100 | 20 | 0000 | |||||||||||||
26 | ori rd, rs1, imm | 0b110 | 0b010101 | 21 | 0000 | ||||||||||||||
27 | andi rd, rs1, imm | 0b111 | 0b010110 | 22 | 0000 | ||||||||||||||
28 | sb rs2, offset(rs1) | S | 0b0100011 | 0b000 | 0b010111 | 23 | 0000 | ||||||||||||
29 | sh rs2, offset(rs1) | 0b001 | 0b011000 | 24 | 0000 | ||||||||||||||
30 | sw rs2, offset(rs1) | 0b010 | 0b011001 | 25 | 0000 | ||||||||||||||
31 | beq rs1, rs2, offset | SB | 0b1100011 | 0b000 | 0b011010 | 26 | 0000 | ||||||||||||
32 | bne rs1, rs2, offset | 0b001 | 0b011011 | 27 | 0000 | ||||||||||||||
33 | blt rs1, rs2, offset | 0b100 | 0b011100 | 28 | 0000 | ||||||||||||||
34 | bge rs1, rs2, offset | 0b101 | 0b011101 | 29 | 0000 | ||||||||||||||
35 | bltu rs1, rs2, offset | 0b110 | 0b011110 | 30 | 0000 | ||||||||||||||
36 | bgeu rs1, rs2, offset | 0b111 | 0b011111 | 31 | 0000 | ||||||||||||||
37 | auipc rd, offset | U | 0b0010111 | 0b100000 | 32 | 0000 | |||||||||||||
38 | lui rd, offset | 0b0110111 | 0b100001 | 33 | 0000 | ||||||||||||||
39 | jal rd, imm | UJ | 0b1101111 | 0b100010 | 34 | 0000 | |||||||||||||
40 | jalr rd, rs1, imm | I | 0b1100111 | 0b000 | 0b100011 | 35 | 0000 | ||||||||||||
41 | csrw rd, csr, rs1 | CSR | 0b1110011 | 0b001 | 0b100100 | 36 | 0000 | ||||||||||||
42 | csrwi rd, csr, uimm | 0b101 | 0b100101 | 37 | 0000 | ||||||||||||||