Chip DW1000 pinout

	A	B	C	D	E	F	G
1	category	Pin name	active	pin number	dir	DESCRIPTION

2	undef	NC		1	in	Not used in normal operation. Do not connect.
3	undef	NC		2	in	Not used in normal operation. Do not connect.
4	CLK	EXTCLK		3	in	Reference crystal input or external reference overdrive pin.
5	CLK	XTAL2		4	in	Reference crystal input. Leave floating if external clock is used.
6	PWR	VREF		5	in	Used for on-chip reference current generation. Must be connected to an 11 kΩ (1% tolerance) resistor to ground.
7	PWR	VDDMS		6	out	Output of on-chip regulator to off-chip decoupling capacitor.
8	PWR	VDDIF		7	out	Output of on-chip regulator to off-chip decoupling capacitor.
9	CLK	CLKTUNE		8	in	Clock PLL loop filter connection to off-chip filter components.
10	PWR	VDDCLK		9	out	Output of on-chip regulator to off-chip decoupling capacitor.
11	PWR	VDDSYN		10	out	Output of on-chip regulator to off-chip decoupling capacitor.
12	PWR	VDDVCO		11	out	Output of on-chip regulator to off-chip decoupling capacitor.
13	CLK	VCOTUNE		12	in	RF PLL loop filter connection to off-chip filter components.
14	undef	NC		13	in	Not used in normal operation. Do not connect.
15	undef	NC		14	in	Not used in normal operation. Do not connect.
16	PWR	VDDLNA		15	in	External supply to the receiver LNA.
17	RF	RF_P		16	io	Positive pin of the 100 Ω differential RF pair. Should be AC coupled.
18	RF	RF_N		17	io	Negative pin of the 100 Ω differential RF pair. Should be AC coupled.
19	PWR	VDDPA1		18	in	External supply to the transmitter power amplifier.
20	PWR	VDDPA2		19	in	External supply to the transmitter power amplifier.
21	PWR	VDDREG		20	out	Output of on-chip regulator.
22	Sync	EXTON		21	out	External device enable.
23	undef	FORCEON		22	in	Not used in normal operation. Must be connected to ground
24	WakeUp	WAKEUP		23	in	When asserted into its active high state, the WAKEUP pin brings the DW1000 out of SLEEP or DEEPSLEEP states into operational mode.
25	SPI	SPICSn	Low	24	in	SPI chip select.
26	PWR	VDDAON		25	in	External supply for the Always-On (AON) portion of the chip.
27	PWR	VDDLDOD		26	in	External supply for digital circuits.
28	RST	RSTn	Low	27	in	Reset pin.
29	PWR	VDDIOA		28	in	External supply for digital circuits.
30	GPIO	GPIO7		29	io	The SYNC input pin is used for external synchronization
31	GPIO	GPIO6		30	io	General purpose I/O pin.	pulled low
32	PWR	VDDIO		31	in	Digital IO Ring Decoupling.
33	PWR	VSSIO		32	in	Negative I/O ring supply. Must be connected to ground.
34	GPIO	GPIO5		33	io	General purpose I/O pin.	pulled low
35	GPIO	GPIO4		34	io	General purpose I/O pin.
36	GPIO	GPIO3		35	io	General purpose I/O pin.
37	GPIO	GPIO2		36	io	General purpose I/O pin.
38	GPIO	GPIO1		37	io	General purpose I/O pin.
39	GPIO	GPIO0		38	io	General purpose I/O pin.
40	SPI	SPIMOSI		39	in	SPI data input.
41	SPI	SPIMISO		40	out	SPI data output.
42	SPI	SPICLK		41	in	SPI clock
43	PWR	VDDIO		42	in	Digital IO Ring Decoupling.
44	PWR	VSSIO		43	in	Negative I/O ring supply. Must be connected to ground.
45	PWR	VDDDIG		44	out	Output of on-chip regulator. Connect to VDDREG on PCB. Requires a local 100 nF capacitor to VSSIO.
46	IRQ	IRQ / GPIO8	high	45	out	Interrupt Request output from the DW1000 to the host processor.
47	undef	TESTMODE		46	in	Not used in normal operation. Must be connected to ground.
48	PWR	VDDBATT		47	in	External supply to all other on-chip circuits.
49	PWR	VDDLDOA		48	in	External supply to analog circuits.
50	PWR	GND		49	in	Ground Paddle on underside of package. Must be soldered to the PCB ground plane for thermal and RF performance.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100