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Sharc + Synergy Lab Reading Group Schedule 2022 Fall
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Time: Friday 11:00 am - 12:30 pm
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Location: https://gatech.zoom.us/my/callie.hao
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Note: There is no need to specify a paper title yet -- you can just reserve a slot and fill in the details later.
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DateSlotPresenterTitleAuthors & AfflicationsPublish VenueYearAbstractLink to Slides
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9/2/20221Stefan Abi-KaramSelf-Supervised Learning For Graphs
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9/9/20221No Presentation Today! Let's meet next week. :) Sorry!
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2Feel free to sign up for other slots!
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9/16/20221Divya Kiran KadiyalaClio: a hardware-software co-designed disaggregated memory systemZhiyuan Guo et.al , UCSDASPLOS'222022Clio: a hardware-software co-designed disaggregated memory system | Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating SystemsPresentation Slides: https://gtvault-my.sharepoint.com/:p:/g/personal/dkadiyala3_gatech_edu/EfzX0yOQOmpBuw3hl6t_3h4B0EcIh7csQV1EzPLcN3H5sA?e=tHUZha

Additional:
DirectCXL Paper: https://www.usenix.org/conference/atc22/presentation/gouk
DirectCXL Video: https://www.youtube.com/watch?v=6a5NSMH-7hY&ab_channel=KAISTCAMELab
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2Akshat RamachandranPositIV : A Configurable Posit processor Architecture for Image and Video ProcessingAkshat Ramachandran, John Gustafson et al., VJTI & NUS, SingaporeEuromicro DSD2022Image processing is essential for applications such as robot vision, remote sensing, computational photography, augmented reality etc. In the design of dedicated hardware for such applications, IEEE Std 754TM floating point (float) arithmetic units have been widely used. While float-based architectures have achieved favorable results, their hardware is complicated and requires a large silicon footprint. In this paper we propose a Posit-based Image and Video processor (PositIV), a completely pipelined, configurable, image processor using posit arithmetic that guarantees lower power use and smaller silicon footprint than floats. PositIV is able to effectively overlap computation with memory access and supports multidimensional addressing, virtual border handling, prefetching and buffering. It is suc- cessfully able to integrate configurability, flexibility, and ease of development with real-time performance characteristics. The performance of PositIV is validated on several image processing algorithms for different configurations and compared against state-of-the-art implementations. Additionally, we empirically demonstrate the superiority of posits in processing images for several conventional algorithms, achieving at least 35–40% im- provement in image quality over standard floats.Paper Link: https://ieeexplore.ieee.org/document/9996725
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9/23/20221Hanqiu ChenSampling methods for efficient training of graph
convolutional networks: A survey		Xin Liu et al. Chinese Academy of Sciences
IEEE/CAA Journal of Automatica Sinica'21
https://arxiv.org/abs/2103.05872TBD
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9/30/20221Zhihan XuN3H-Core: Neuron-designed Neural Network
Accelerator via FPGA-based Heterogeneous
Computing Cores		Zhihan Xu et al., Shanghai Jiao Tong Univ.FPGA 2022https://dl.acm.org/doi/10.1145/3490422.3502367
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10/7/20221Yuhong LiWhat Makes Convolutional Models Great on Long Sequence Modeling?
Yuhong Li
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10/14/20221Rishov SarkarAPack: Off-Chip, Lossless Data Compression for Efficient Deep Learning InferenceAlberto Delmas Lascorz et al., University of TorontoarXiv:2201.08830 [cs.AR]2022https://arxiv.org/abs/2201.08830https://gtvault.sharepoint.com/:p:/s/SharcLab/EbC07wsTREdNmxwHBMhl9GIB0OHkk6Ek2rK5pF4yM6meBA?e=iRGhha
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10/21/20221Akshay KamathTowards Grand Unification of Object TrackingBin Yan et al.ECCV 2022
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10/28/20221Hamed SeyedroudbariNightcore: Efficient and Scalable Serverless Computing for Latency-Sensitive, Interactive MicroservicesZhipeng Jia et al.ASPLOS '21
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11/4/20221Shang YangHeuristic Adaptability to Input Dynamics for SpMM on GPUsGuohao Dai et al., Tsinghua Univ.DAC 20222022
https://arxiv.org/abs/2202.08556
Sparse Matrix-Matrix Multiplication (SpMM) has served as fundamental components in various domains. Many previous studies exploit GPUs for SpMM acceleration because GPUs provide high bandwidth and parallelism. We point out that a static design does not always improve the performance of SpMM on different input data (e.g., >85\% performance loss with a single algorithm). In this paper, we consider the challenge of input dynamics from a novel auto-tuning perspective, while following issues remain to be solved: (1) Orthogonal design principles considering sparsity. Orthogonal design principles for such a sparse problem should be extracted to form different algorithms, and further used for performance tuning. (2) Nontrivial implementations in the algorithm space. Combining orthogonal design principles to create new algorithms needs to tackle with new challenges like thread race handling. (3) Heuristic adaptability to input dynamics. The heuristic adaptability is required to dynamically optimize code for input dynamics.
To tackle these challenges, we first propose a novel three-loop model to extract orthogonal design principles for SpMM on GPUs. The model not only covers previous SpMM designs, but also comes up with new designs absent from previous studies. We propose techniques like conditional reduction to implement algorithms missing in previous studies. We further propose DA-SpMM, a Data-Aware heuristic GPU kernel for SpMM. DA-SpMM adaptively optimizes code considering input dynamics. Extensive experimental results show that, DA-SpMM achieves 1.26x~1.37x speedup compared with the best NVIDIA cuSPARSE algorithm on average, and brings up to 5.59x end-to-end speedup to applications like Graph Neural Networks.
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11/11/20221
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11/18/20221Asmer Hamid AliAn FPGA Implementation of Deep Spiking Neural Networks
for Low-Power and Fast Classification		Xiping Ju et al.
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11/25/20221
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12/2/20221
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12/9/20221
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12/16/20221Ninad JangleA Hardware/Software Co-Design Vision for Deep Learning at the Edge
F. Ponzina, S. Machetti, M. Rios, B. W. Denkinger, A. Levisse, G. Ansaloni, M. Peon-Quir ´ os, D. Atienza
IEEE Micro2022https://www.researchgate.net/publication/362502122_A_hardwaresoftware_Co-Design_Vision_for_Deep_Learning_At_the_Edge
https://docs.google.com/presentation/d/1XTZIozqQCn4qeSHD78GazNbA73nwPjqH/edit?usp=sharing&ouid=114294662162462639944&rtpof=true&sd=true
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