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DC-SCI Pin Definition 
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The DC-SCI connector pinout includes the single name (preferred board net name that include functional and directional nomenclature), gold finger lengths, single node usages, voltage, direction, typical usages and dual node usage.
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The contact sequence for each pin indicates the order in which the pins make contact between the HPM and the DC-SCM. The GND pins are required to be long pins or 1st mate. The PRSNT0_N/ PRSNT1_N pins and P12V_AUX pins are required to be short pins or 2nd mate. However, the remaining pins indicated as 2nd mate can be flexibly assigned as long pins/1st mate if dictated by design or DFM requirements.
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Multi-function DC-SCI pins list the functions in order starting with the most typical expected usage.
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When multiple voltages are listed for a signal, they map the respective alternate pin function order.
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DC-SCI Signal Descriptions 
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The following sections provide the signal descriptions of signals through the DC-SCI. 
The signal names are constructed using the notation of:
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 function_(bus source)_(signal source)_(signal destination)_Instance#_Node#_Polarity  
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 Node 1 omits the Node #. Functions with only 1 instance do not include 0. Polarity of active low uses the *_N naming.
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Note: Follow device datasheet recommendations to appropriately terminate un-used signals on the DC-SCM. 
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Abbreviation Definition: 
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Symbol Description
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_N or #  Denotes active low signal
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Input  Input to DC-SCM
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Output  Output from DC-SCM
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InOut At least one of the functions is a bidirectional signal
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CHANGES MADE
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6/30/2021A65-A66, B65- B66 to PCIe Lane only - USB Host controller;
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A65-A66, B65- B66 Fixed Dual Node had wrong directions
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OA1-OB13 - Removed PCIe X4 and GNDs
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A14 from GND to FRU_ONLY_VCC_SCM_HPM = 3.3VAUX
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B8 - dual node is GPIO primary function since ESPI_ALERT0 is embedded in eSPI IO1 by spec
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OA8-OA13 - Moved JTAG away from being overloaded with SPI1_SCMCNTRL. Many agreed on decoupling
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A8-A12 - made JTAG only
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A62-A63 showed incorrect singel node alt function as dual node input clock. Cleaned up
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Added the missing Dual Nide Direction column for connector B side missing before!
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Problem - QSPI1 had IO2 & IO3 @ 3.3V & other 5 pins at proper 1.8V. Swapped A58-A59 (now 1.8V) with B68-B69 (now 3.3V). This means dual partition loses 1 Hybrid I2C_I3C bus in place of QSPI IO2 and IO3 being the right voltage!
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Swapped A54-A57 -now I2C_I3C_1V8 with B52-B55 Now TPM for P0
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Changed A70 from unnecessary GND to GPIO
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Changed B50 from alt function of RX_ER to only primary function of GPIO
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Made OB6 = 1 ADC as this helps with various use cases like rail readings, analog typing of inventory
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A28- removed GPI alt function as HPM_SCM PERST is expected in all cases
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Swapped A-B33-34 with AB65-66 so that the lanes are near the clock for sought and northbound PCIe links. Better grouping
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B63 - Changed from 3.3V to 0V since that is the asserted state and the de-asserted state is HPM circuit specific to enable eFuse
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A60 - changed GPIO to GPI since in dual partition, it is input only
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Added NCSI2 (NOTE that NCSI2 is currently available only in single node).
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B8 - Changed to GPO only
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B9-B10 added to dual partition the same eSPI CS1+ALERT1 as on singlde node since thay may be a viable pin usage in dual
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B9-B10 - changed typo from I3C_1V8_4_* to I3C_1V8_3_ since there was no 3 and there is a total of 4 dedicated I3Cs starting with bus #0.
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B43-B49 - Added GPIOs as secondary function on NCSI bus #1…for those trying to ween off of NC-SI
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B36-B37 & B68-B69 Add 3rd alt function for 1 company wanting the 2 BMC USB busses instead to be 2 Host busses (very atypical).
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Moves PCIE_HPM_SCM_PERST_P1_N to OB12 so that NCSI2 is not mutually exclusive with dual parition AND since the P1 PCIe links are nearby.
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7/1/2021A39-A42 - changed I3C bus 0 and 1 from 1.8V to 1.0/1.2V and changed alt function names to accommodate FSI and other companies who asked for a mix.
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7/3/2021B57-B60. Added 2 3.3V I2C busses as primary function on dual node since they were lost with NCSI2 add inadvertently.
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Co-located all NCSI2 signals over I2C
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Fixed SCM_HPM_STBY_EN out of PCIe region and back to B61 (my miss earlier on the X4 PCIe and STBY_EN being exclusive). Note this is not exactly next to B63 PRSTN since a pin short between these 2 important signals would not be good
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Freed up A63 as GPIO
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7/9/2021Cleaned up names for P1 as still QSPI0 and ESPI0
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Renumbered the I2C_3V3_ busses since #7 was missing as it had converted
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7/21/2021Swpped SCM_SPI and JTAG - since JTAG can be accomplished through means such as USB to JTAG initiator, HPM FPGA initiator, etc. but BMC SPI cannot due to immutabel nature of usages with HPM FPGAs
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Added USB3 as the 2ndary function with PCIe X1 intended for USB host controller on DC-SCM (per HPE request relate to PCIe lane usage and desiring USB host controller on HPM - versus loopback).
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Merged the X4's upper 2 lanes as the secondary function for single node to unify back to 1 table
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Added columns for single node lowest power state that allows bias on each pin - as discussed in discovery workstream
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FRU VCC supply - added that 200mA max into the netname!
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7/23/2021Reverted to PCIe X4; merged JTAG and SPI_SCMCNTRL back; dropped nice to have ADC1; Moved PCIE_HPM_SCM_PERST_P1_N to A63
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7/28/2021Moved PCIE_HPM_SCM_PERST_P1_N from A63 back to orginal with NCSI2 on B58…pending IBM approval of not needing dual node AND NCSI2
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Updated all pinlengths to 1 for GND and 0.5 for all others.
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8/4/2021Per IBM request, made B52-B58 the same between single and dual partition, which meant to move P1 PERST to the last GPIO.
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8/6/2021Decoupled JTAG (old home) and SPI1_SCMCTRL (to B59-B63)
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Moved SPI0 TPM for Partition 0 to be exclusive with QSPI0_HPMCTRL_*P1*
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Retasked B51 GND to GPIO / NCSI2_SCM_HPM_EN since NCSI2 and dual partition were wanted at the same time
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B8 removed GPIO as all want ALERT0 (since generally eSPI CS1 would terminate on HPM requiring ALERT0)
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8/8/2021Top PCIe x4 – all lanes available in Dual Node as well. We’d like to keep all the PCIe x4 lanes in the Dual Node as well. The reason is that we connect 2 x PCIe x2 anyway to the top PCIex4 in Dual Node. This combination can also work as PCIe x4 if needed when board is in Single Node mode. Anyway PCIe allows for a lot of flexibility there’s no need to limit that in Dual Node. Theoretically this interface should allow for bifurcation if needed as well, there’s no need to tie it to fixed x4 in the spec.
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Swapped A14 VCC_SCM_HPM_FRU with B50 SCM_HPM_STBY_EN. The justification is to avoid any cross talk on the STBY_EN (located between 2 x NCSI interfaces) and collocate it with STBY_RST. FRU VSS will have caps anyway and any cross talk will not be an issue.
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Avoid dual voltage on B52 – B55 -- To avoid dual voltage on the NCSI2 and I2C_I3C we swapped B39 – B42 3.3V I2C interfaces with B52 – B55 I2C_I3C_1V8.
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8/9/2021Removed PCIe duplicates - so changed BMC and USB host PCIe lanes to #4 and #5.
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A51-S52 - Made primary dual parition function = I3C instead of GPIO
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Clarified USB2.0 port usage options, inclusive of adding *_BMC_* to the OTG one.
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OFFICIALLY NAMING FILE Version 0.94
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8/15/2021Fixed A33-B34 Power domain clarifications
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Removed TRST note since polarity inversion is not needed with JTAG & SPI decoupling
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Clarified A68-B69 USB and PCIe clock power domains
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8/24/2021 0.95cFixed SPI pin directions (bug)
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0.95bFixed B59 alt function from GPI to GPO to match the primary function (technically GPIO could work on any signal like this)
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0.95bClarified the power domains for the USB ports
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" "B47 Add UART1_HPM_SCM_RX
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" "B48 Add UART1_HPM_SCM_TX
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" "B51 - Add UART0_HPM_SCM_RX
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" "A63 - Add UART0_HPM_SCM_TX
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" "A60 Added alt function of SPI1_IRQ0_N to make SPI1 random access not polled.
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0.95dUpdated PECI voltage as a range copied from DC-SCMv1 spec vs simply 1.0
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" "Added MAIN Tab for overview
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9/15/21 0.95eAesthethic cleanup. Nothing substantive
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Removed the 0 from ESPI0 and QSPI0 since neither have a "1" instance.
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10/3/2021 0.95fFixed nomencalture from parition to node
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Changed SPI0 to SPI_HPMCNTRL; SPI1 to SPI_SCMCNTRL*; fixed name for GPI / SPI_HPM_SCM_IRQ0_N; other aesthetic only mods.
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10/12/2021 0.95g Removed voltages from LTPI and PCIe since they aren't DC 1.8V.; Fixed missing A69 clock name; Clarified USB2.0 power domains for each of the exclusive modes/directions); Addded some dual node stats
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10/25/2021 0.95h Updated I2C_I3C naming and bus numbering; Swapped UART1 RX and TX to better align with the direction of the 2 alt functions
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11/9/2021 0.95i Removed HPM_SCM on UART0 and UART1 4 pins since link partners are peers and not a controller / target relationship. Making signal names more generic.
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11/9/2021 0.95j Added UART directions in the direction column AND swapped UART0 and UART1 RX and TX to match the direction of the other functions on those 2 pins.
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11/18/2021 0.95kFixed truncated name to: UART1_TX, removing HPM_SCM since either direction is supported
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11/19/2021 0.95lChanged the alternative function order for SPI_HPMCNTRL_TPM_CS_N to match I2C_I3C_1V8_10 signals as first alternative.
Changed the name of SPI_SCMCNTRL_IRQ0_N to indicate the IRQ0 is related to immutable SPI terface.
Changed the names of LVDS to LTPI and fixed the naming convention to SRC_DST approach.
Changed the UART0/1 names to follow SRC_DST naming convention.
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1/10/2022 0.95mAdded alt functions of SGMII, USB3 and LTPI2 on PCIe X4
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1/19/2022 0.95nAdded alt functions of USB3 and LTPI2 on PCIe X4 for Dual node with updated power states definitions. SGMII is not added for dual node due to high number of alt-functions.
bug fix: removed _1 for I2C_19
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3/28/2022 0.95o Remove LTPI_DATA2 and 3 - not necessary or requested by anyone.
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Fixed USB3_SCMROOT to USB3_SCMHOST for proper nomenclature
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Change name B36-37 from USB2_SCMHOST_DN to USB2_SCMHOST1_DN. Same for dual node
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Change name B68-69 from USB2_BMC_SCMOTG to USB2_SCMHOST2. Same for dual node
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Add USB2_SCMROOT3 to OB11-OB12