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Timing AnalysisStatus
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Setup Timing Check clean across all scenarios
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Hold Timing Check clean across all scenarios
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Recovery Check clean across all scenarios
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Remove Check clean across all scenarios
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Max Trans clean across all scenarios
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Max Cap clean across all scenarios
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Crosstalk clean across all scenarios
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Interface Timing
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Constraints Verified with the FE team
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Log Files Errors and warnings thoroughly reviewed
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Power Integrity
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Dynamic Voltage Drop under the spec
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Static Voltage Drop under the spec
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Power EM
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Signal EM
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Instances disconencted from the power grid
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SPR above the spec
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Log Files Errors and warnings thoroughly reviewed
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Power Analysis
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Dynamic Power under the spec for all use-cases
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Leakage Power under the spec
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Annotation percentage from SAIF file > 99%
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Power Recovery attempted
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Log Files Errors and warnings thoroughly reviewed
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DRCs, ERCs, LVS
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Design Rule Checks Clean
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Layout versus Schematic
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Electrical Rule Checks Clean
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Thermal, SI, EMI, ESD
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Thermal Analysis Done and location of therm sensors reviewed
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Signal Integrity Anlaysis
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EMI Analysis
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ESD analysis and ESD clamp spec reviewed
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Functional Verification
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Functional Test Coverage Targets Achieved
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GLS Clean
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