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Color Legend:Identified Active Work Item
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Gaps / Possible Future Work
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Completed AI ItemsWhere is this driven at in OCP?
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Deprecated / No go / Not Applicable
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Project SectorProjectWorkitemSC PriorityCurrent StatusExpected CompletionNarrativePoCNew Workstream?OCP Project OCP Sub-ProjectPL Priority
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DC IT InfrastructureServerMHS Open System for AIEarly discussions on what areas / ingredients to focus on under the umbrella of MHS.​Taking similar approach as DC-MHs but expanding to include accelerators, semantic and scale-out NW, etc.Shawn.Dube@dell.com
brian.d.aspnes@intel.com		​
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NIC 3.x - AI form factorsOCP NIC 3.x DSFF nearing completion. Need next steps.​Similar to smart NIC but AI accleration.dchong@meta.com
thomas1.ng@intel.com		​
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AI HW/SW Codesign Whitepaper Pending​Whitepaper just published (late Sept 24). The follow through of graduating from FTI to OCP group to persue following up on the WP concepts is 4Q24,1Q25none​
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Composable InfrastructureCMS has launched an AI workstream. Need next steps.​manoj.wadekar@ocproject.net
srajadnya@microsoft.com		Yes​
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Quantization (OFP8)1.0 Complete - https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-12-01-pdf-1​​
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Quantization (MX)1.0 Complete- https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf​​
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Chiplets for AINot Started. Need next steps.​AI specific chiplets and requirements such as faster BoW line rates, encouraging AI IP blocks to join, acclerator blocks etc...Anu.Ramamurthy@microchip.com
jawad@paloaltoelectron.com		​
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System in Package Security (SiP)Caliptra....OCP and Linux Foundation. Could this be extended to support chiplets? Collaboration between Open Chiplets and Security project.​There is some concern about the ability about supply chain security such as counterfit components, misbehaving blocks and the leaving it easy to hack the SiP/components (substrate attacks etc...) An opportunity exists to define risks/best practices even define solutions in this area.​
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Common/Standardized Hardware Abstraction layersNot Started. Need next steps.​Software layers to abstract component(s) from AI technical stack such that developers may have hetrogeneous accleration components for AI without developing bespoke interfaces for each- this will grow the ecosystem. Could be in conjunction with AI SW-HW Co-design FTI group.Software layers and definitions. Work with OPF/HW MGt aspects such as firmware etc...kasper.wszolek@intel.com​
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In-Memory ComputationNot Started. Need next steps.​There is an FTS DCC group looking at this in additon to the CMS group. manoj.wadekar@ocproject.net​
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Rack Scale-Up / Scale-Out Network Protocol(s)Protocols likely defined outside of OCP; ie: UALink, UEC, NVLink​​
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Nvidia GB200 NVL-72 RackNot aligned with Open Systems for AI initiative. Was a fine contribution but not necessarily a point of long term innovation.​John Norton <johnn@nvidia.com>​
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Common/Standardized Hardware Abstraction layers (MHS) Combined with work above.​kasper.wszolek@intel.com​
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OAI Re-designAbsorbed/accounted for as part of MHS Open System for AI thinking.​brian.d.aspnes@intel.com ​
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CoolingASIC Cooling TechniquesNot Started. Need next steps.​Probably splits into near (OCP) and long term (FTI)tejas1.shah@intel.comYes​
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NetworkingFTI Short Reach Optical InterconnectWhitepaper in process (ETA: 5/15)​In progress with FTI group SROIron.swartzentruber@ocproject.net​
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CSIG (with UEC)UEC is working on CSIC Spec (ETA: 10/24)​Starting up within Networkingbarak.gafni@ocproject.net
ravindra.sunkad@ocproject.net		Yes​
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Falcon + NVME + RDMAFalcon 0.9 - Gathering Feedback - 1.0 Expected Q3​GoogleYes​
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AI Driven Load balancingNot Started. Need next steps.​Using telemetry/HW MGT to control networking and compute resources. Possibly requires Digital Twins.noneYes​
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Co-packaged Copper and/or Co-packaged OpticsNot Started. Need next steps.​One aspect (link types) In progress with FTI group Short Reach Optical Interconnect (SROI). Also could branch into useful implementations across server and networking none​
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224G+ SerDesThis is an IEEE standards body piece of work.​There are changing requirements from 56G->112G->224G regarding board design requirements, layouts etc...
This item is for study and any recommendations for implementation.
Scope is to follow IEEE standards progress for for incorporation into next gen server design		thomas1.ng@intel.comNo​
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NIC 3.0 (AI NIC form factors)Combine/grouped together with NIC 3.x - AI Form Factors above in Server project​thomas1.ng@intel.comNo​
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Rack Scale-Up / Scale-Out Network(s) - Physical detailsCombine/grouped together with NIC 3.x - AI Form Factors above in Server project​​
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StorageFTI Data Centric ComputingOngoing whitepaper draft in FTI. New WG name for what used to be Computational Storage.​Minimizing data movement, intelligent clusteringyangseok.ki@samsung.com​
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Computational StorageFolded into and renamed to Data Centric Computing covered above.​Multiple efforts have taken place over the years on this topic. While it has not been of immediate interest to OCP Community due to maturity, ambuigity etc... evolution of the idea continues and it's a potential architecture that we should take a defintive position on and if so, establish the community to implement​
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SecurityChiplets (Chiplets as a Security Device)Not Started. Need next steps.​There are layers to security and one layer may inclide application/data layer that can be accelerated in SiP/chiplet. Here is a distant example: https://ieeexplore.ieee.org/document/10286457 and https://ieeexplore.ieee.org/document/10466542bryankel@microsoft.com, jeffandersen@google.com​
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In-memory encryptionNot Started. Need next steps.​​
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SAFE Outside StorageNot Started. Need next steps.​bryankel@microsoft.com, jeffandersen@google.com​
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Project SectorProjectWorkitemSC PriorityCurrent StatusExpected CompletionNarrativePoCNew Workstream?OCP Project OCP Sub-ProjectPL Priority
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DC Physical InfrastructureDC FacilitiesOCP Ready AI VersionEarly Discussion​mailto:mark.dansie@opencompute.orgOCP Ready DC Recognition Program​
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DCF Sustainability (Green Concrete) Started in Project​​
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AI Driven Facility ManagementNot Started​This might be best paired with Digital Twins. The goal is to automate and maximize efficiency via AI loops of control systems such as DCIM etc...​
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Power Co-Generation (Alliances)Not Started​Not enough power and/or not enough economically available power. Co-located generation will help with this​
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Enhanced Heat Re-UseNot Started​The first level hasn't been widely achieved- redirection of heat to coolants for downstream uses. More work to be done to make this widely adopted. Next level is doing more work (active work) with heat than transfering to a fluid (passive work)jaime.comella@aq-compute.com​
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TCS​Modularize the steps on Liquid Cooling such that instead of bespoke cooling designs for DCs, there is a far higher degree of standardization/commonality such that scales of economy helpDon.Mitchell@victaulic.com​
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Rack and PowerAI Rack (200 - 250KW) (Power)Scheduled for development after June 6th Update​harry.soin@ocproject.net, daniel.g.cartagena@intel.com YesRack and PowerHPR Rack for AI Infra​
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AI Rack (200 - 250KW) (Cooling)Not Started​gpcharest@meta.comYesRack and PowerHPR Rack for AI Infra​
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AI Rack (200 - 250KW) (Power Rail)Not Started​gpcharest@meta.comYesRack and PowerHPR Rack for AI Infra​
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AI Rack (200 - 250KW) (Frame)Scheduled for development after June 6th Update​steven.moore@ocproject.netYesRack and PowerHPR Rack for AI Infra​
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AI Rack 48VDC PowerPresented at OCP Global Summit 2024- Work in progress​​
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Advanced Power Architecture AI Rack 400VPresented at OCP Global Summit 2024- Work in progress​​
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Advanced Power Architecture AI Rack 800VPresented at OCP Global Summit 2024- Work in progress​​
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AI Rack (300 - 500 KW) (Power)Not Started​N+2 AI Acceleration components llikely require 2X the power/heat transfer than next gen (N) acceleration chips do. Racks need to be designed now to support this.daniel.g.cartagena@intel.comYesRack and PowerHPR Rack for AI Infra​
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AI Rack (300 - 500 KW) (Cooling)Not Started​N+2 AI Acceleration components likely require 2X the power/heat transfer than next gen (N) acceleration chips do. Racks need to be designed now to support this.YesRack and PowerHPR Rack for AI Infra​
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AI Rack (300 - 500 KW) (Power Rail)Not Started​YesRack and PowerHPR Rack for AI Infra​
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AI Rack (300 - 500 KW) (Frame)Not Started​YesRack and PowerHPR Rack for AI Infra​
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AI Rack (300kW - 1MW) (Cooling) (OCP Global Summit MS- Mt.Diablo)(OCP Global Summit MS- Mt.Diablo shared)2Q 2025​
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AI Rack (300kW - 1MW) (Cooling)(OCP Global Summit MS- Mt.Diablo shared)2Q 2025​
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AI Rack (300kW - 1MW) (Cooling)(OCP Global Summit MS- Mt.Diablo shared)2Q 2025​
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CoolingAdvanced Cooling Facilities (500kw+) (400VDC)Not Started​​
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Project SectorProjectWorkitemSC PriorityCurrent StatusExpected CompletionNarrativePoCNew Workstream?OCP Project OCP Sub-ProjectPL Priority
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Systems ManagmentHardware ManagementRAS (Silent Data Corruption)v1.0 contribution from non-public CLA workstream​jeyork@google.comNoHW ManagementServer Component Resilience WS​
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RAS (GPU & Accelerator RAS Requirements) v1.0 contribution from non-public CLA workstream​jeyork@google.comNoHW ManagementGPU Management WS​
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GPU HW Management (GPU & Accelerator Management Interfaces) v1.0 contribution from non-public CLA workstream​jeyork@google.comNoHW ManagementGPU Management WS​
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GPU HW Management (Firmware Update Specification)v1.0 contribution from non-public CLA workstream​jeyork@google.comNoHW ManagementGPU Management WS​
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Rack Management - Composable Disaggregated InfrastructureDrafting OpenRMC v1.2​Extending the prescription of rack management to include the composition service. The Redfish profile to v1.1 is posted. An GoLang implement of the rack manager which conforms to the profile is on the OCP respository.hanwang@meta.comNoHW ManagementOpenRMC-DM Subproject​
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Rack Management - PDUDrafts exists, awaiting Rack & Power specification to reference​Prescribing management of the rack. Redfish profiles be drafted for the Rack PDU, and the Power ShelfNoHW ManagementProfiles WS​
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Liquid Cooling ManagementDrafting Spec and Profile​Prescribing management of liquid cooling elements. Redfish profiles being drafted for Liquid Cooling Baseline, Cooling Distribution Unit (CDU), and the Rear Door Heat Exchangermike.jones@vertiv.comNoCooling EnvironmentsHW Mgmt for Liquid Cooling WS​
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Standardize Hardware Abstraction layers [JL] Remove DC-MHS parenthetical. Organization doesn't need to be specified. Kasper states that this can be considered "under development". The MHS Plug and Play WS v0.3 has been released.​Software layers to abstract specific component from AI technical stack such that developers may have hetrogeneous accleration components for AI without developing bespoke interfaces for each (like system device drivers)- this will grow the ecosystem. With server group. Focus on the OPF/HW MGt aspects such as firmware etc.kasper.wszolek@intel.comNoServerDC-MHS​
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Fleet ManagementEarly drafting​Fleet management of 100K nodes. Covers lifecycle, configuration, telemetry, and controlsammy.nachimuthu@ocproject.netNoHW ManagementCloud Service Model WS​
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GPU HW Management Stack (Tooling & Telemetry)Not Started or no visibility​Far more work can be done to create a hetrogeneous approach to AI accelerator management- meaning finer grained measurements, more meaningful measurements, and standardization across AI accelerator architectures/products​
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AI Driven Automated Management (Digital Twins)Not Started​Session to be held in AI track at Global Summit 2024 by Cadence team. Digital Twins to better manage the DC both for deployment and operations​
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AI System Orchestration (Alliance with Linux Foundation)Not Started​Integration of FOSS orchestration layers with OCP hardware. Some of the above steps would be towards this direction.​
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Standarized Hardware Abstraction layers (OAI) [JL] Combined with the DC-MHS entry (row 64)​Software layers for OAI to abstract component from AI technical stack such that developers may have hetrogeneous accleration components for AI without developing bespoke interfaces for each- this will grow the ecosystem. Could be in conjunction with AI SW-HW Co-design FTI group. Focus on the OPF/HW MGt aspects such as firmware etc...​
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Test and ValidationAI Hardware System BenchmarkingNot Started​Need to standardize on measurements for AI performance. For example, how to define a 1EXFLOP system (what measures are used etc...) Definitions, templates and best practices​
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HW MGT section has been verified by JL and he concurs with the work items
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