Open Source Chip Design Hack Chat
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http://hackaday.io/hackchat
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NameHackaday.io profileQuestion
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LukelrenaudTo what degree is your workflow open source, verses your proccess. Cadence, Synopsis, and MGC have made major strides in modernizing their tools in the last few years, where do the open source equivelents sit? In s a similar vein, how do foundary NDAs play into an open-source flow and implementation?
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BradybradysalzI think it's safe to say it's easier to open source some RTL than a mixed-signal/analog IC. Similar to Luke's question, how do you go about open sourcing analog stuff? Release schematics (sizing, device type), layout, GDS, etc...
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NathannwkChisel is used for the reference implementation of RISC-V. What are the benefits of Chisel over a traditional RTL HDL such as VHDL or Verilog?
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NathannwkHow does RISC-V compare to other cores such as ARM Cortex M1 or MicroBlaze on an (Xilinx Artix-7 or Kintex-7) FPGA in terms of computational performance, power consumption, and resource utilization (equivalent gates / LUTs)?
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