Parallax Propeller 2 Instructions v32 (multi-sheet)
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1
#S = immediate (I=1). S = register.
#D = immediate (L=1). D = register.

- Assembly Syntax -
* Z = (result == 0).
** If #S and cogex, PC += signed(S). If #S and hubex, PC += signed(S*4). If S, PC = register S.

- Description -
8-Cog Timing
* +1 if crosses hub long

- Cogex Cycles -
8-Cog Timing
* +1 if crosses hub long

- Hubex Cycles -
* Data not forwarded.

- Register Write -
- Hub R/W -- Stack R/W -
CF/ZF are local bits
Dv = variable to write

- Spin Methods -
2
<empty> {#}D,{#}S<empty>
3
<empty> {#}D,{#}S<empty>
4
ABS D {WC/WZ/WCZ}Get absolute value of D into D. D = ABS(D). C = D[31]. *2sameDABS_(Dv)
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ABS D,{#}S {WC/WZ/WCZ}Get absolute value of S into D. D = ABS(S). C = S[31]. *2sameDABS_(Dv,S)
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ADD D,{#}S {WC/WZ/WCZ}Add S into D. D = D + S. C = carry of (D + S). *2sameDADD_(Dv,S)
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8
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Add S into D, signed. D = D + S. C = correct sign of (D + S). *2sameDADDS_(Dv,S)
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Add (S + C) into D, signed and extended. D = D + S + C. C = correct sign of (D + S + C). Z = Z AND (result == 0).2sameDADDSX_(Dv,S)
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Add (S + C) into D, extended. D = D + S + C. C = carry of (D + S + C). Z = Z AND (result == 0).2sameDADDX_(Dv,S)
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AKPIN {#}SAcknowledge smart pin S[5:0].2sameAKPIN_(S)
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ALLOWIAllow interrupts (default).2sameALLOWI_
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ALTB DAlter D field of next instruction to D[13:5].2sameD
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ALTB D,{#}SAlter D field of next instruction to (D[13:5] + S) & \$1FF. D += sign-extended S[17:9].2sameD
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ALTD DAlter D field of next instruction to D[8:0].2sameD
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ALTD D,{#}SAlter D field of next instruction to (D + S) & \$1FF. D += sign-extended S[17:9].2sameD
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ALTGB DAlter subsequent GETBYTE/ROLBYTE instruction. Next S field = D[10:2], N field = D[1:0].2sameD
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ALTGB D,{#}SAlter subsequent GETBYTE/ROLBYTE instruction. Next S field = (D[10:2] + S) & \$1FF, N field = D[1:0]. D += sign-extended S[17:9].2sameD
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ALTGN DAlter subsequent GETNIB/ROLNIB instruction. Next S field = D[11:3], N field = D[2:0].2sameD
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ALTGN D,{#}SAlter subsequent GETNIB/ROLNIB instruction. Next S field = (D[11:3] + S) & \$1FF, N field = D[2:0]. D += sign-extended S[17:9].2sameD
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ALTGW DAlter subsequent GETWORD/ROLWORD instruction. Next S field = D[9:1], N field = D[0].2sameD
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ALTGW D,{#}SAlter subsequent GETWORD/ROLWORD instruction. Next S field = ((D[9:1] + S) & \$1FF), N field = D[0]. D += sign-extended S[17:9].2sameD
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ALTI DExecute D in place of next instruction. D stays same.2sameD
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ALTI D,{#}SSubstitute next instruction's I/R/D/S fields with fields from D, per S. Modify D per S.2sameD
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ALTR DAlter result register address (normally D field) of next instruction to D[8:0].2sameD
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ALTR D,{#}SAlter result register address (normally D field) of next instruction to (D + S) & \$1FF. D += sign-extended S[17:9].2sameD
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ALTS DAlter S field of next instruction to D[8:0].2sameD
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ALTS D,{#}SAlter S field of next instruction to (D + S) & \$1FF. D += sign-extended S[17:9].2sameD
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ALTSB DAlter subsequent SETBYTE instruction. Next D field = D[10:2], N field = D[1:0].2sameD
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ALTSB D,{#}SAlter subsequent SETBYTE instruction. Next D field = (D[10:2] + S) & \$1FF, N field = D[1:0]. D += sign-extended S[17:9].2sameD
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ALTSN DAlter subsequent SETNIB instruction. Next D field = D[11:3], N field = D[2:0].2sameD
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ALTSN D,{#}SAlter subsequent SETNIB instruction. Next D field = (D[11:3] + S) & \$1FF, N field = D[2:0]. D += sign-extended S[17:9].2sameD
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ALTSW DAlter subsequent SETWORD instruction. Next D field = D[9:1], N field = D[0].2sameD
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ALTSW D,{#}SAlter subsequent SETWORD instruction. Next D field = (D[9:1] + S) & \$1FF, N field = D[0]. D += sign-extended S[17:9].2sameD
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AND D,{#}S {WC/WZ/WCZ}AND S into D. D = D & S. C = parity of result. *2sameDAND_(Dv,S)
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ANDN D,{#}S {WC/WZ/WCZ}
AND !S into D. D = D & !S. C = parity of result. *2sameDANDN_(Dv,S)
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AUGS #NQueue #N[31:9] to be used as upper 23 bits for next #S occurrence, so that the next 9-bit #S will be augmented to 32 bits.2same
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BITC D,{#}S {WCZ}Bit S[4:0] of D = C, C,Z = D[S[4:0]].2sameDBITC_(Dv,S)
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BITH D,{#}S {WCZ}Bit S[4:0] of D = 1, C,Z = D[S[4:0]].2sameDBITH_(Dv,S)
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BITL D,{#}S {WCZ}Bit S[4:0] of D = 0, C,Z = D[S[4:0]].2sameDBITL_(Dv,S)
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BITNC D,{#}S {WCZ}Bit S[4:0] of D = !C, C,Z = D[S[4:0]].2sameDBITNC_(Dv,S)
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BITNOT D,{#}S {WCZ}Bit S[4:0] of D = !bit, C,Z = D[S[4:0]].2sameDBITNOT_(Dv,S)
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BITNZ D,{#}S {WCZ}Bit S[4:0] of D = !Z, C,Z = D[S[4:0]].2sameDBITNZ_(Dv,S)
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BITRND D,{#}S {WCZ}Bit S[4:0] of D = RND, C,Z = D[S[4:0]].2sameDBITRND_(Dv,S)
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BITZ D,{#}S {WCZ}Bit S[4:0] of D = Z, C,Z = D[S[4:0]].2sameDBITZ_(Dv,S)
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BLNPIX D,{#}SAlpha-blend bytes of S into bytes of D, using SETPIV value.7sameDBLNPIX_(Dv,S)
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BMASK DGet LSB-justified bit mask of size (D[4:0] + 1) into D. D = (\$0000_0002 << D[4:0]) - 1.2sameDBMASK_(Dv)
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BMASK D,{#}SGet LSB-justified bit mask of size (S[4:0] + 1) into D. D = (\$0000_0002 << S[4:0]) - 1.2sameDBMASK_(Dv,S)
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BRK {#}DIf in debug ISR, set next break condition to D. Else, trigger break if enabled, conditionally write break code to D[7:0].2sameBRK_(D)
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CALL #ACall to A by pushing {C, Z, 10'b0, PC[19:0]} onto stack. If R = 1, PC += A, else PC = A.413...20Push
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CALL D {WC/WZ/WCZ}Call to D by pushing {C, Z, 10'b0, PC[19:0]} onto stack. C = D[31], Z = D[30], PC = D[19:0].413...20Push
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CALLA #ACall to A by writing {C, Z, 10'b0, PC[19:0]} to hub long at PTRA++. If R = 1, PC += A, else PC = A.14...32 *Write
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CALLA D {WC/WZ/WCZ}Call to D by writing {C, Z, 10'b0, PC[19:0]} to hub long at PTRA++. C = D[31], Z = D[30], PC = D[19:0].14...32 *Write
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CALLB #ACall to A by writing {C, Z, 10'b0, PC[19:0]} to hub long at PTRB++. If R = 1, PC += A, else PC = A.14...32 *Write
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CALLB D {WC/WZ/WCZ}Call to D by writing {C, Z, 10'b0, PC[19:0]} to hub long at PTRB++. C = D[31], Z = D[30], PC = D[19:0].14...32 *Write
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CALLD D,{#}S {WC/WZ/WCZ}
Call to S** by writing {C, Z, 10'b0, PC[19:0]} to D. C = S[31], Z = S[30].413...20D
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CALLD PA/PB/PTRA/PTRB,#ACall to A by writing {C, Z, 10'b0, PC[19:0]} to PA/PB/PTRA/PTRB (per W). If R = 1, PC += A, else PC = A.413...20Per W
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CALLPA {#}D,{#}SCall to S** by pushing {C, Z, 10'b0, PC[19:0]} onto stack, copy D to PA.413...20PAPush
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CALLPB {#}D,{#}SCall to S** by pushing {C, Z, 10'b0, PC[19:0]} onto stack, copy D to PB.413...20PBPush
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CMP D,{#}S {WC/WZ/WCZ}
Compare D to S. C = borrow of (D - S). Z = (D == S).2sameCMP_(D,S)
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CMPM D,{#}S {WC/WZ/WCZ}
Compare D to S, get MSB of difference into C. C = MSB of (D - S). Z = (D == S).2sameCMPM_(D,S)
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CMPR D,{#}S {WC/WZ/WCZ}
Compare S to D (reverse). C = borrow of (S - D). Z = (D == S).2sameCMPR_(D,S)
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CMPS D,{#}S {WC/WZ/WCZ}
Compare D to S, signed. C = correct sign of (D - S). Z = (D == S).2sameCMPS_(D,S)
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CMPSUB D,{#}S {WC/WZ/WCZ}
Compare and subtract S from D if D >= S. If D => S then D = D - S and C = 1, else D same and C = 0. *2sameDCMPSUB_(Dv,S)
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CMPSX D,{#}S {WC/WZ/WCZ}
Compare D to (S + C), signed and extended. C = correct sign of (D - (S + C)). Z = Z AND (D == S + C).2sameCMPSX_(D,S)
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CMPX D,{#}S {WC/WZ/WCZ}
Compare D to (S + C), extended. C = borrow of (D - (S + C)). Z = Z AND (D == S + C).2sameCMPX_(D,S)
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COGATN {#}DStrobe "attention" of all cogs whose corresponging bits are high in D[15:0].2sameCOGATN_(D)
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COGBRK {#}DIf in debug ISR, trigger asynchronous breakpoint in cog D[3:0]. Cog D[3:0] must have asynchronous breakpoint enabled.2sameCOGBRK_(D)
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COGID {#}D {WC}If D is register and no WC, get cog ID (0 to 15) into D. If WC, check status of cog D[3:0], C = 1 if on.sameD if reg and !WCCOGID_(D/Dv)
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COGINIT {#}D,{#}S {WC}Start cog selected by D. S[19:0] sets hub startup address and PTRB of cog. Prior SETQ sets PTRA of cog.sameD if reg and WCCOGINIT_(Dv,S{,Q})
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COGSTOP {#}DStop cog D[3:0].sameCOGSTOP_(D)
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CRCBIT D,{#}SIterate CRC value in D using C and polynomial in S. If (C XOR D[0]) then D = (D >> 1) XOR S, else D = (D >> 1).2sameDCRCBIT_(Dv,S)
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CRCNIB D,{#}SIterate CRC value in D using Q[31:28] and polynomial in S. Like CRCBIT, but 4x. Q = Q << 4. Use SETQ+CRCNIB+CRCNIB+CRCNIB...2sameDCRCNIB_(Dv,S)
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DECMOD D,{#}S {WC/WZ/WCZ}
Decrement with modulus. If D = 0 then D = S and C = 1, else D = D - 1 and C = 0. *2sameDDECMOD_(Dv,S)
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DECOD DDecode D[4:0] into D. D = 1 << D[4:0].2sameDDECOD_(Dv)
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DECOD D,{#}SDecode S[4:0] into D. D = 1 << S[4:0].2sameDDECOD_(Dv,S)
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DIRC {#}D {WCZ}DIR bit of pin D[5:0] = C. C,Z = DIR bit.2sameDIRxDIRC_(D)
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DIRH {#}D {WCZ}DIR bit of pin D[5:0] = 1. C,Z = DIR bit.2sameDIRxDIRH_(D)
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DIRL {#}D {WCZ}DIR bit of pin D[5:0] = 0. C,Z = DIR bit.2sameDIRxDIRL_(D)
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DIRNC {#}D {WCZ}DIR bit of pin D[5:0] = !C. C,Z = DIR bit.2sameDIRxDIRNC_(D)
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DIRNOT {#}D {WCZ}DIR bit of pin D[5:0] = !bit. C,Z = DIR bit.2sameDIRxDIRNOT_(D)
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DIRNZ {#}D {WCZ}DIR bit of pin D[5:0] = !Z. C,Z = DIR bit.2sameDIRxDIRNZ_(D)
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DIRRND {#}D {WCZ}DIR bit of pin D[5:0] = RND. C,Z = DIR bit.2sameDIRxDIRRND_(D)
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DIRZ {#}D {WCZ}DIR bit of pin D[5:0] = Z. C,Z = DIR bit.2sameDIRxDIRZ_(D)
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DJF D,{#}SDecrement D and jump to S** if result is \$FFFF_FFFF.2 or 13...20D
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DJNF D,{#}SDecrement D and jump to S** if result is not \$FFFF_FFFF.2 or 13...20D
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DJNZ D,{#}SDecrement D and jump to S** if result is not zero.2 or 13...20D
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DJZ D,{#}SDecrement D and jump to S** if result is zero.2 or 13...20D
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DRVC {#}D {WCZ}OUT bit of pin D[5:0] = C. DIR bit = 1. C,Z = OUT bit.2sameDIRx* + OUTxDRVC_(D)
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DRVH {#}D {WCZ}OUT bit of pin D[5:0] = 1. DIR bit = 1. C,Z = OUT bit.2sameDIRx* + OUTxDRVH_(D)
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DRVL {#}D {WCZ}OUT bit of pin D[5:0] = 0. DIR bit = 1. C,Z = OUT bit.2sameDIRx* + OUTxDRVL_(D)
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DRVNC {#}D {WCZ}OUT bit of pin D[5:0] = !C. DIR bit = 1. C,Z = OUT bit.2sameDIRx* + OUTxDRVNC_(D)
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DRVNOT {#}D {WCZ}OUT bit of pin D[5:0] = !bit. DIR bit = 1. C,Z = OUT bit.2sameDIRx* + OUTxDRVNOT_(D)
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DRVNZ {#}D {WCZ}OUT bit of pin D[5:0] = !Z. DIR bit = 1. C,Z = OUT bit.2sameDIRx* + OUTxDRVNZ_(D)
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DRVRND {#}D {WCZ}OUT bit of pin D[5:0] = RND. DIR bit = 1. C,Z = OUT bit.2sameDIRx* + OUTxDRVRND_(D)
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DRVZ {#}D {WCZ}OUT bit of pin D[5:0] = Z. DIR bit = 1. C,Z = OUT bit.2sameDIRx* + OUTxDRVZ_(D)
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ENCOD D {WC/WZ/WCZ}Get bit position of top-most '1' in D into D. D = position of top '1' in S (0..31). C = (S != 0). *2sameDENCOD_(Dv)