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1 | #S = immediate (I=1). S = register. #D = immediate (L=1). D = register. - Assembly Syntax - | * Z = (result == 0). ** If #S and cogex, PC += signed(S). If #S and hubex, PC += signed(S*4). If S, PC = register S. - Description - | 8-Cog Timing * +1 if crosses hub long - Cogex Cycles - | 8-Cog Timing * +1 if crosses hub long - Hubex Cycles - | * Data not forwarded. - Register Write - | - Hub R/W - | - Stack R/W - | CF/ZF are local bits Dv = variable to write - Spin Methods - | |||||||||||||||||||
2 | <empty> {#}D,{#}S | <empty> | |||||||||||||||||||||||||
3 | <empty> {#}D,{#}S | <empty> | |||||||||||||||||||||||||
4 | ABS D {WC/WZ/WCZ} | Get absolute value of D into D. D = ABS(D). C = D[31]. * | 2 | same | D | ABS_(Dv) | |||||||||||||||||||||
5 | ABS D,{#}S {WC/WZ/WCZ} | Get absolute value of S into D. D = ABS(S). C = S[31]. * | 2 | same | D | ABS_(Dv,S) | |||||||||||||||||||||
6 | ADD D,{#}S {WC/WZ/WCZ} | Add S into D. D = D + S. C = carry of (D + S). * | 2 | same | D | ADD_(Dv,S) | |||||||||||||||||||||
7 | ADDCT1 D,{#}S | Set CT1 event to trigger on CT = D + S. Adds S into D. | 2 | same | D | ADDCT1_(Dv,S) | |||||||||||||||||||||
8 | ADDCT2 D,{#}S | Set CT2 event to trigger on CT = D + S. Adds S into D. | 2 | same | D | ADDCT2_(Dv,S) | |||||||||||||||||||||
9 | ADDCT3 D,{#}S | Set CT3 event to trigger on CT = D + S. Adds S into D. | 2 | same | D | ADDCT3_(Dv,S) | |||||||||||||||||||||
10 | ADDPIX D,{#}S | Add bytes of S into bytes of D, with $FF saturation. | 7 | same | D | ADDPIX_(Dv,S) | |||||||||||||||||||||
11 | ADDS D,{#}S {WC/WZ/WCZ} | Add S into D, signed. D = D + S. C = correct sign of (D + S). * | 2 | same | D | ADDS_(Dv,S) | |||||||||||||||||||||
12 | ADDSX D,{#}S {WC/WZ/WCZ} | Add (S + C) into D, signed and extended. D = D + S + C. C = correct sign of (D + S + C). Z = Z AND (result == 0). | 2 | same | D | ADDSX_(Dv,S) | |||||||||||||||||||||
13 | ADDX D,{#}S {WC/WZ/WCZ} | Add (S + C) into D, extended. D = D + S + C. C = carry of (D + S + C). Z = Z AND (result == 0). | 2 | same | D | ADDX_(Dv,S) | |||||||||||||||||||||
14 | AKPIN {#}S | Acknowledge smart pin S[5:0]. | 2 | same | AKPIN_(S) | ||||||||||||||||||||||
15 | ALLOWI | Allow interrupts (default). | 2 | same | ALLOWI_ | ||||||||||||||||||||||
16 | ALTB D | Alter D field of next instruction to D[13:5]. | 2 | same | D | ||||||||||||||||||||||
17 | ALTB D,{#}S | Alter D field of next instruction to (D[13:5] + S) & $1FF. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
18 | ALTD D | Alter D field of next instruction to D[8:0]. | 2 | same | D | ||||||||||||||||||||||
19 | ALTD D,{#}S | Alter D field of next instruction to (D + S) & $1FF. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
20 | ALTGB D | Alter subsequent GETBYTE/ROLBYTE instruction. Next S field = D[10:2], N field = D[1:0]. | 2 | same | D | ||||||||||||||||||||||
21 | ALTGB D,{#}S | Alter subsequent GETBYTE/ROLBYTE instruction. Next S field = (D[10:2] + S) & $1FF, N field = D[1:0]. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
22 | ALTGN D | Alter subsequent GETNIB/ROLNIB instruction. Next S field = D[11:3], N field = D[2:0]. | 2 | same | D | ||||||||||||||||||||||
23 | ALTGN D,{#}S | Alter subsequent GETNIB/ROLNIB instruction. Next S field = (D[11:3] + S) & $1FF, N field = D[2:0]. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
24 | ALTGW D | Alter subsequent GETWORD/ROLWORD instruction. Next S field = D[9:1], N field = D[0]. | 2 | same | D | ||||||||||||||||||||||
25 | ALTGW D,{#}S | Alter subsequent GETWORD/ROLWORD instruction. Next S field = ((D[9:1] + S) & $1FF), N field = D[0]. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
26 | ALTI D | Execute D in place of next instruction. D stays same. | 2 | same | D | ||||||||||||||||||||||
27 | ALTI D,{#}S | Substitute next instruction's I/R/D/S fields with fields from D, per S. Modify D per S. | 2 | same | D | ||||||||||||||||||||||
28 | ALTR D | Alter result register address (normally D field) of next instruction to D[8:0]. | 2 | same | D | ||||||||||||||||||||||
29 | ALTR D,{#}S | Alter result register address (normally D field) of next instruction to (D + S) & $1FF. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
30 | ALTS D | Alter S field of next instruction to D[8:0]. | 2 | same | D | ||||||||||||||||||||||
31 | ALTS D,{#}S | Alter S field of next instruction to (D + S) & $1FF. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
32 | ALTSB D | Alter subsequent SETBYTE instruction. Next D field = D[10:2], N field = D[1:0]. | 2 | same | D | ||||||||||||||||||||||
33 | ALTSB D,{#}S | Alter subsequent SETBYTE instruction. Next D field = (D[10:2] + S) & $1FF, N field = D[1:0]. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
34 | ALTSN D | Alter subsequent SETNIB instruction. Next D field = D[11:3], N field = D[2:0]. | 2 | same | D | ||||||||||||||||||||||
35 | ALTSN D,{#}S | Alter subsequent SETNIB instruction. Next D field = (D[11:3] + S) & $1FF, N field = D[2:0]. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
36 | ALTSW D | Alter subsequent SETWORD instruction. Next D field = D[9:1], N field = D[0]. | 2 | same | D | ||||||||||||||||||||||
37 | ALTSW D,{#}S | Alter subsequent SETWORD instruction. Next D field = (D[9:1] + S) & $1FF, N field = D[0]. D += sign-extended S[17:9]. | 2 | same | D | ||||||||||||||||||||||
38 | AND D,{#}S {WC/WZ/WCZ} | AND S into D. D = D & S. C = parity of result. * | 2 | same | D | AND_(Dv,S) | |||||||||||||||||||||
39 | ANDN D,{#}S {WC/WZ/WCZ} | AND !S into D. D = D & !S. C = parity of result. * | 2 | same | D | ANDN_(Dv,S) | |||||||||||||||||||||
40 | AUGS #N | Queue #N[31:9] to be used as upper 23 bits for next #S occurrence, so that the next 9-bit #S will be augmented to 32 bits. | 2 | same | |||||||||||||||||||||||
41 | BITC D,{#}S {WCZ} | Bit S[4:0] of D = C, C,Z = D[S[4:0]]. | 2 | same | D | BITC_(Dv,S) | |||||||||||||||||||||
42 | BITH D,{#}S {WCZ} | Bit S[4:0] of D = 1, C,Z = D[S[4:0]]. | 2 | same | D | BITH_(Dv,S) | |||||||||||||||||||||
43 | BITL D,{#}S {WCZ} | Bit S[4:0] of D = 0, C,Z = D[S[4:0]]. | 2 | same | D | BITL_(Dv,S) | |||||||||||||||||||||
44 | BITNC D,{#}S {WCZ} | Bit S[4:0] of D = !C, C,Z = D[S[4:0]]. | 2 | same | D | BITNC_(Dv,S) | |||||||||||||||||||||
45 | BITNOT D,{#}S {WCZ} | Bit S[4:0] of D = !bit, C,Z = D[S[4:0]]. | 2 | same | D | BITNOT_(Dv,S) | |||||||||||||||||||||
46 | BITNZ D,{#}S {WCZ} | Bit S[4:0] of D = !Z, C,Z = D[S[4:0]]. | 2 | same | D | BITNZ_(Dv,S) | |||||||||||||||||||||
47 | BITRND D,{#}S {WCZ} | Bit S[4:0] of D = RND, C,Z = D[S[4:0]]. | 2 | same | D | BITRND_(Dv,S) | |||||||||||||||||||||
48 | BITZ D,{#}S {WCZ} | Bit S[4:0] of D = Z, C,Z = D[S[4:0]]. | 2 | same | D | BITZ_(Dv,S) | |||||||||||||||||||||
49 | BLNPIX D,{#}S | Alpha-blend bytes of S into bytes of D, using SETPIV value. | 7 | same | D | BLNPIX_(Dv,S) | |||||||||||||||||||||
50 | BMASK D | Get LSB-justified bit mask of size (D[4:0] + 1) into D. D = ($0000_0002 << D[4:0]) - 1. | 2 | same | D | BMASK_(Dv) | |||||||||||||||||||||
51 | BMASK D,{#}S | Get LSB-justified bit mask of size (S[4:0] + 1) into D. D = ($0000_0002 << S[4:0]) - 1. | 2 | same | D | BMASK_(Dv,S) | |||||||||||||||||||||
52 | BRK {#}D | If in debug ISR, set next break condition to D. Else, trigger break if enabled, conditionally write break code to D[7:0]. | 2 | same | BRK_(D) | ||||||||||||||||||||||
53 | CALL #A | Call to A by pushing {C, Z, 10'b0, PC[19:0]} onto stack. If R = 1, PC += A, else PC = A. | 4 | 13...20 | Push | ||||||||||||||||||||||
54 | CALL D {WC/WZ/WCZ} | Call to D by pushing {C, Z, 10'b0, PC[19:0]} onto stack. C = D[31], Z = D[30], PC = D[19:0]. | 4 | 13...20 | Push | ||||||||||||||||||||||
55 | CALLA #A | Call to A by writing {C, Z, 10'b0, PC[19:0]} to hub long at PTRA++. If R = 1, PC += A, else PC = A. | 14...32 * | Write | |||||||||||||||||||||||
56 | CALLA D {WC/WZ/WCZ} | Call to D by writing {C, Z, 10'b0, PC[19:0]} to hub long at PTRA++. C = D[31], Z = D[30], PC = D[19:0]. | 14...32 * | Write | |||||||||||||||||||||||
57 | CALLB #A | Call to A by writing {C, Z, 10'b0, PC[19:0]} to hub long at PTRB++. If R = 1, PC += A, else PC = A. | 14...32 * | Write | |||||||||||||||||||||||
58 | CALLB D {WC/WZ/WCZ} | Call to D by writing {C, Z, 10'b0, PC[19:0]} to hub long at PTRB++. C = D[31], Z = D[30], PC = D[19:0]. | 14...32 * | Write | |||||||||||||||||||||||
59 | CALLD D,{#}S {WC/WZ/WCZ} | Call to S** by writing {C, Z, 10'b0, PC[19:0]} to D. C = S[31], Z = S[30]. | 4 | 13...20 | D | ||||||||||||||||||||||
60 | CALLD PA/PB/PTRA/PTRB,#A | Call to A by writing {C, Z, 10'b0, PC[19:0]} to PA/PB/PTRA/PTRB (per W). If R = 1, PC += A, else PC = A. | 4 | 13...20 | Per W | ||||||||||||||||||||||
61 | CALLPA {#}D,{#}S | Call to S** by pushing {C, Z, 10'b0, PC[19:0]} onto stack, copy D to PA. | 4 | 13...20 | PA | Push | |||||||||||||||||||||
62 | CALLPB {#}D,{#}S | Call to S** by pushing {C, Z, 10'b0, PC[19:0]} onto stack, copy D to PB. | 4 | 13...20 | PB | Push | |||||||||||||||||||||
63 | CMP D,{#}S {WC/WZ/WCZ} | Compare D to S. C = borrow of (D - S). Z = (D == S). | 2 | same | CMP_(D,S) | ||||||||||||||||||||||
64 | CMPM D,{#}S {WC/WZ/WCZ} | Compare D to S, get MSB of difference into C. C = MSB of (D - S). Z = (D == S). | 2 | same | CMPM_(D,S) | ||||||||||||||||||||||
65 | CMPR D,{#}S {WC/WZ/WCZ} | Compare S to D (reverse). C = borrow of (S - D). Z = (D == S). | 2 | same | CMPR_(D,S) | ||||||||||||||||||||||
66 | CMPS D,{#}S {WC/WZ/WCZ} | Compare D to S, signed. C = correct sign of (D - S). Z = (D == S). | 2 | same | CMPS_(D,S) | ||||||||||||||||||||||
67 | CMPSUB D,{#}S {WC/WZ/WCZ} | Compare and subtract S from D if D >= S. If D => S then D = D - S and C = 1, else D same and C = 0. * | 2 | same | D | CMPSUB_(Dv,S) | |||||||||||||||||||||
68 | CMPSX D,{#}S {WC/WZ/WCZ} | Compare D to (S + C), signed and extended. C = correct sign of (D - (S + C)). Z = Z AND (D == S + C). | 2 | same | CMPSX_(D,S) | ||||||||||||||||||||||
69 | CMPX D,{#}S {WC/WZ/WCZ} | Compare D to (S + C), extended. C = borrow of (D - (S + C)). Z = Z AND (D == S + C). | 2 | same | CMPX_(D,S) | ||||||||||||||||||||||
70 | COGATN {#}D | Strobe "attention" of all cogs whose corresponging bits are high in D[15:0]. | 2 | same | COGATN_(D) | ||||||||||||||||||||||
71 | COGBRK {#}D | If in debug ISR, trigger asynchronous breakpoint in cog D[3:0]. Cog D[3:0] must have asynchronous breakpoint enabled. | 2 | same | COGBRK_(D) | ||||||||||||||||||||||
72 | COGID {#}D {WC} | If D is register and no WC, get cog ID (0 to 15) into D. If WC, check status of cog D[3:0], C = 1 if on. | same | D if reg and !WC | COGID_(D/Dv) | ||||||||||||||||||||||
73 | COGINIT {#}D,{#}S {WC} | Start cog selected by D. S[19:0] sets hub startup address and PTRB of cog. Prior SETQ sets PTRA of cog. | same | D if reg and WC | COGINIT_(Dv,S{,Q}) | ||||||||||||||||||||||
74 | COGSTOP {#}D | Stop cog D[3:0]. | same | COGSTOP_(D) | |||||||||||||||||||||||
75 | CRCBIT D,{#}S | Iterate CRC value in D using C and polynomial in S. If (C XOR D[0]) then D = (D >> 1) XOR S, else D = (D >> 1). | 2 | same | D | CRCBIT_(Dv,S) | |||||||||||||||||||||
76 | CRCNIB D,{#}S | Iterate CRC value in D using Q[31:28] and polynomial in S. Like CRCBIT, but 4x. Q = Q << 4. Use SETQ+CRCNIB+CRCNIB+CRCNIB... | 2 | same | D | CRCNIB_(Dv,S) | |||||||||||||||||||||
77 | DECMOD D,{#}S {WC/WZ/WCZ} | Decrement with modulus. If D = 0 then D = S and C = 1, else D = D - 1 and C = 0. * | 2 | same | D | DECMOD_(Dv,S) | |||||||||||||||||||||
78 | DECOD D | Decode D[4:0] into D. D = 1 << D[4:0]. | 2 | same | D | DECOD_(Dv) | |||||||||||||||||||||
79 | DECOD D,{#}S | Decode S[4:0] into D. D = 1 << S[4:0]. | 2 | same | D | DECOD_(Dv,S) | |||||||||||||||||||||
80 | DIRC {#}D {WCZ} | DIR bit of pin D[5:0] = C. C,Z = DIR bit. | 2 | same | DIRx | DIRC_(D) | |||||||||||||||||||||
81 | DIRH {#}D {WCZ} | DIR bit of pin D[5:0] = 1. C,Z = DIR bit. | 2 | same | DIRx | DIRH_(D) | |||||||||||||||||||||
82 | DIRL {#}D {WCZ} | DIR bit of pin D[5:0] = 0. C,Z = DIR bit. | 2 | same | DIRx | DIRL_(D) | |||||||||||||||||||||
83 | DIRNC {#}D {WCZ} | DIR bit of pin D[5:0] = !C. C,Z = DIR bit. | 2 | same | DIRx | DIRNC_(D) | |||||||||||||||||||||
84 | DIRNOT {#}D {WCZ} | DIR bit of pin D[5:0] = !bit. C,Z = DIR bit. | 2 | same | DIRx | DIRNOT_(D) | |||||||||||||||||||||
85 | DIRNZ {#}D {WCZ} | DIR bit of pin D[5:0] = !Z. C,Z = DIR bit. | 2 | same | DIRx | DIRNZ_(D) | |||||||||||||||||||||
86 | DIRRND {#}D {WCZ} | DIR bit of pin D[5:0] = RND. C,Z = DIR bit. | 2 | same | DIRx | DIRRND_(D) | |||||||||||||||||||||
87 | DIRZ {#}D {WCZ} | DIR bit of pin D[5:0] = Z. C,Z = DIR bit. | 2 | same | DIRx | DIRZ_(D) | |||||||||||||||||||||
88 | DJF D,{#}S | Decrement D and jump to S** if result is $FFFF_FFFF. | 2 or 13...20 | D | |||||||||||||||||||||||
89 | DJNF D,{#}S | Decrement D and jump to S** if result is not $FFFF_FFFF. | 2 or 13...20 | D | |||||||||||||||||||||||
90 | DJNZ D,{#}S | Decrement D and jump to S** if result is not zero. | 2 or 13...20 | D | |||||||||||||||||||||||
91 | DJZ D,{#}S | Decrement D and jump to S** if result is zero. | 2 or 13...20 | D | |||||||||||||||||||||||
92 | DRVC {#}D {WCZ} | OUT bit of pin D[5:0] = C. DIR bit = 1. C,Z = OUT bit. | 2 | same | DIRx* + OUTx | DRVC_(D) | |||||||||||||||||||||
93 | DRVH {#}D {WCZ} | OUT bit of pin D[5:0] = 1. DIR bit = 1. C,Z = OUT bit. | 2 | same | DIRx* + OUTx | DRVH_(D) | |||||||||||||||||||||
94 | DRVL {#}D {WCZ} | OUT bit of pin D[5:0] = 0. DIR bit = 1. C,Z = OUT bit. | 2 | same | DIRx* + OUTx | DRVL_(D) | |||||||||||||||||||||
95 | DRVNC {#}D {WCZ} | OUT bit of pin D[5:0] = !C. DIR bit = 1. C,Z = OUT bit. | 2 | same | DIRx* + OUTx | DRVNC_(D) | |||||||||||||||||||||
96 | DRVNOT {#}D {WCZ} | OUT bit of pin D[5:0] = !bit. DIR bit = 1. C,Z = OUT bit. | 2 | same | DIRx* + OUTx | DRVNOT_(D) | |||||||||||||||||||||
97 | DRVNZ {#}D {WCZ} | OUT bit of pin D[5:0] = !Z. DIR bit = 1. C,Z = OUT bit. | 2 | same | DIRx* + OUTx | DRVNZ_(D) | |||||||||||||||||||||
98 | DRVRND {#}D {WCZ} | OUT bit of pin D[5:0] = RND. DIR bit = 1. C,Z = OUT bit. | 2 | same | DIRx* + OUTx | DRVRND_(D) | |||||||||||||||||||||
99 | DRVZ {#}D {WCZ} | OUT bit of pin D[5:0] = Z. DIR bit = 1. C,Z = OUT bit. | 2 | same | DIRx* + OUTx | DRVZ_(D) | |||||||||||||||||||||
100 | ENCOD D {WC/WZ/WCZ} | Get bit position of top-most '1' in D into D. D = position of top '1' in S (0..31). C = (S != 0). * | 2 | same | D | ENCOD_(Dv) |