ABCDEFGHIJKLMNOPQRSTUVWXYZ
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easy
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hard
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done
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Fix regressions from bugzilla
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86121 NVIDIA backlight not workingBruno Prémont <bonbons@linux-vserver.org>ce027dac592c vgaarb: Don't default exclusively to first video device with mem+io

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85491 radeon 0000:01:00.0: Fatal error during GPU initYinghai Lu <yinghai@kernel.org>5b28541552ef PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources
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85311 radeon power management issue
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Fix bugs from bugzilla
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Fix Coverity issueshttps://scan.coverity.com/projects/linux?tab=overview
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Remove arch dependencies from drivers/pci/host/KconfigMost host controller drivers are now arch-independent
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Remove __u32, __u16, __u8 from drivers/pciDone by Logan GunthorpeAssuming that's the right thing to do, of course
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Profile and optimize quirks -- Paul Menzel's "pci_apply_final_quirks() taking half a second"See https://lkml.kernel.org/r/44cada166e42007d27b4c3e3aa0744d7@molgen.mpg.de
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Figure out _OSC issue\_SB_.PCI0:_OSC invalid UUID, _OSC request data:1 1e 0I don't believe all these machines have invalid UUIDs
https://bugzilla.kernel.org/show_bug.cgi?id=94661
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Taint kernel for pci= parametersUsers shouldn't have to use command-line parameters. We should be able to figure things out automatically.Prarit started this
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Taint kernel on userspace config writes
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Use pci_walk_bus() in PMESeveral pci_walk_bus() reimplementations in PME. Using pci_walk_bus() directly would avoid that and reduce use of pci_bus_sem
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Print bridge windows in logical order when enumeratingCurrently we print the bridge, then the downstream devices, then the windows of the bridge leading to them, which is confusing. Maybe this would allow us to validate and claim downstream resources at the time we enumerate the device, too.pci 0000:00:1c.3: [8086:3420] type 01 class 0x060400
pci 0000:04:00.0: [1033:0194] type 00 class 0x0c0330
pci 0000:04:00.0: reg 0x10: [mem 0xfe800000-0xfe803fff 64bit]
pci 0000:00:1c.3: PCI bridge to [bus 04]
pci 0000:00:1c.3: bridge window [mem 0xfe800000-0xfe9fffff]
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Restructure PCIe support so it's not a driverpcie_portdrv_init() uses pci_register_driver() to claim PCIe switch devices, which means a driver for device-specific switch functionality, e.g., performance monitoring, cannot use pci_register_driver() to claim the device. I think the portdrv functionality (PME, AER, hotplug, virtual channel) should be built into the core instead of being handled as a driver.This would also resolve the issue that we rely on link ordering so that pcie_portdrv_init() happens before pcied_init()
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Initialize pciehp during enumeration
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Simplify pciehp state machineCollect all inputs once, don't bother decoding in ISR (do all decoding in work queue)See Guenter's patches: https://patchwork.ozlabs.org/patch/539218/ and discussion
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Warn about hosts that can only do 32-bit config accessesMake it consistent across drivers
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Do MPS configuration (pcie_bus_configure_settings()) alwaysCurrently some drivers skip this when PCI_PROBE_ONLY
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Configure MPS/MRRS during enumeration
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Configure ASPM during enumeration
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Figure out _OSC issue
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Attach device to IOMMU during enumerationAn IOMMU should be discovered before the devices that use it. But I don't think that's always the case today.
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Cache option ROM during enumerationBIOSes often don't allocate address space for option ROMs because they don't think the OS needs them. Linux then tries to reassign space for the ROMs so, e.g., virtualized guests can read them. This often messes up space allocation for other devices because the host bridge doesn't have enough resources to assign all the device space and all the option ROM space simultaneously.<bjorn> aw: we have this perennial problem where a BIOS doesn't assign space for an option ROM, linux tries to shuffle things to make space, then we run out of space for other things
<bjorn> aw: what if we read the option ROM at enumeration-time and cached it, so we could later use the cached copy rather than actually mapping the ROM BAR?
<bjorn> what sort of issues would we trip over if we did that?
<aw> bjorn: only thing I can think of is that rom updates would be an issue
<aw> generally those require a reboot anyway, but the mechanism might be difficult if it involves the rom
<aw> scares the crap out of me when people report that they assigned a device to a windows VM and did a firmware update, but QEMU caches the rom too
<bjorn> a reboot? unless the linux driver relies on the option ROM having been executed, it seems like a device reset should be enough
<aw> I agree, but that's typically achieved via a reboot and maybe therefore to keep the instructions simple, most seem indicate a reboot is required
<aw> would you use one of the bar mappings to map the rom and refresh the cache on every reset?
<aw> some devices are going to have device specific reset methods that the pci core doesn't know about
<bjorn> i don't have any code or even a design, so refreshing a cache on every reset seems possible. of course that wouldn't catch the device-specific resets done by the driver
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Get rid of pci_bridge_check_ranges()pci_read_bridge_bases() already does most of that work; why do we need to do more in pci_bridge_check_ranges()?
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Rename pcie_cap_has_sltctl(), etc., so they are more generic (they're used for capabilities, control, and status registers, not just control).
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Drop default resources for PCI host bridges
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Stop blindly probing for PCI buses (when we have ACPI to tell us about host bridges)
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Turn off AMD IO ECS tweaking
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Audit direct PCIe capability usage in drivers. Most of this should be done via core interfaces.
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Use PCIe capability accessors in mtip_disable_link_opts()
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Cache common capability offsets in struct pci_deve.g., we should look up PCI_CAP_ID_EXP once during enumeration, then use dev->pcie_cap instead of calling pci_find_capability() every time we need it. PCI_EXT_CAP_ID_ERR is another good example
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tg3_chip_reset() sets MPS directly, which might conflict with system settings
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Merge Device Serial Number patches (previously posted).https://lwn.net/Articles/585138/
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Add PCI_NUM_BARS or similarPCI_STD_RESOURCE_END is error-prone and requires "i <=" loops rather than the typical "i <".
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Deprecate mmap on /proc/bus/pci/.../sys/devices/pci*/.../resourceN is a better interface.
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Convert pci_resource_to_user() to a weak functionThen we can get rid of the HAVE_ARCH_PCI_RESOURCE_TO_USER #define
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Fix pci_sriov_resource_alignment()This actually sizes the BAR again, which is stupid. We shouldn't have to read the BAR again, and sizing it means we'll print its info again in dmesg, which is just confusing. I think it would be better to save the alignment somewhere else, maybe in struct pci_sriov.
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Remove struct hotplug_slot_info and pci_hp_change_slot_info()This is basically a cache that's used when the driver doesn't supply get/set methods. Only a few drivers use pci_hp_change_slot_info().
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Use IS_ENABLED(<config option>) instead of #ifdefProbably not worth doing just by itself. See http://lkml.iu.edu//hypermail/linux/kernel/1204.3/00081.html. Note that the compiler sees the body of an "if (IS_ENABLED(...))" statement, so it must not reference things that are conditionally compiled, e.g., structure elements under an #ifdef. But "#if IS_ENABLED()" is probably safe.
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lspci: Add support for Multicast capability (0x12)
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lspci: Add support for Secondary PCIe capability (0x19)
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lspci: Add support for undecoded capabilitiesMRIOV, MCAST, REBAR, DPA, PMUX, etc.
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lspci: Add support for more DevCap2 fieldsFred
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lspci: Add more symbolic capability names to setpcidonehttps://git.kernel.org/pub/scm/utils/pciutils/pciutils.git/commit/?id=b8f7cd649e4f
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lspci: Make disabled bridge window display consistentI think we print "none" or "empty"; why aren't these the same?see show_range()
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lspci: Add support for dumping from AIDA64 log files and pci=earlydump dmesgBjorn has preliminary patches for AIDA64 support
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lspci: Hexdump vendor-specific capabilities, at least small ones (with -vv or similar)
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lspci: Taint kernel on setpci usage
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lspci: Optimize "lspci -n""strace lspci -n" shows that lspci reads /usr/share/misc/pci.ids even though it doesn't use the data. Could this be optimized?
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lspci: Optimize "lspci -s""strace lspci -s02:00.0" shows that lspci scans the sysfs files for all the PCI devices in the system, even though we only asked for one. Could this be optimized?
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Make host drivers more consistent in structure and namingdra7xx_pcie_host_init(), xgene_pcie_setup(), rcar_pcie_enable, etc.
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Add pci_info(), pci_err(), etc.Several examples in the tree already for other subsystems
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Simplify portdrv IRQ setupfrom Christoph:Note that we should probably replace the irqs array with one storing the relative vector number and use pci_request_irq(). In fact in that case we could probably just pass said array to pcie_message_numbers() to further simplify it.
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Simplify port service driver dmesg loggingInstead of using dev_printk() on the service driver, use dev_printk() on the pci_dev. Can set dev_fmt as necessary.
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Rename pcie_aer_get_firmware_first(); apparently it's a predicate?
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Optimize next_fn() by caching ARI cap offset
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Remove PCI_EXP_DEVCTL_BCR_FLR uses from drivers by using core interfaces
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Move core-only interfaces out of include/linux/pci.hnothing to do here
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Write script to identify new uses of config accessors outside PCI corecould run daily on linux-next
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Remove pci_enable_pcie_error_reporting() usage from driversPCI core should take care of enabling/disabling AER automatically
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Merge linux/aer.h into linux/pci.h
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Merge linux/pci-ats.h into linux/pci.h
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Merge linux/pci-dma.h into linux/pci.h
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Merge linux/pcieport_if.h into drivers/pci/pci.h
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Audit users of linux/pci_hotplug.h
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Program RCB for every device during enumerationCurrently we only do this for _HPX
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Organize linux/pci.hMove things to drivers/pci/pci.h when possible, organize stuff by AER, ATS, PASID, etc. move linux/pcieport_if.h to drivers/pci
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Add #define for Multi-Function Device
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Get rid of pcibios_enable_device()There are several implementations, but nothing really arch-specific.
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Clean up PCI_EXP_LNKCAP_SLS usage in drivers/infiniband/hw/hfi1/pcie.cFred may work on this week of 3/26/2018
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Use pci_name() when possibleSome dev_name() uses in drivers/pci could be pci_name()
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pci_scan_bridge_extend() takes both pci_bus and pci_dev. Does it need both?
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Fix Rui's ASPM issueSee https://lkml.kernel.org/r/1504772799-15173-1-git-send-email-rui_feng@realsil.com.cn
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Connect resource usage, e.g., add_list in setup-bus.c, with struct pci_bus instead of passing it around everywhere
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Replace "PCI_BRIDGE_RESOURCES + 0" with something more descriptivee.g., PCI_BRIDGE_IO_RESOURCE
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Add some sort of pci_dev_is_legacy_vga() interfaceSee PCI_CLASS_DISPLAY_VGA usage
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Remove driver-local definitions of PCI_COMMAND, etcSee drivers/net/fddi/skfp/h/skfbi.h
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Move PCIE_BUS_PEER2PEER and other constants to drivers/pci/pci.hMost are simple, but PCIE_BUS_PEER2PEER does require some sort of tweak to
arch/arm/mach-cns3xxx/pcie.c
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Support _OSC control of LTRSee PCI Firmware Spec r3.2
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Audit use of PCIe internals in driversPCI_EXP_LNKCTL, PCI_EXP_DEVCTL, etc.
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Maybe split PM-related stuff from drivers/pci/pci.c to a new pm.c file?There is already a drivers/pci/pcie/pme.c, which is PCIe-specific
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Maybe split PCIe-related stuff from drivers/pci/pci.c to a new file?
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ASPM projectBetter integrate into enumeration flow, i.e., discover device X, configure device X. Currently pcie_aspm_init_link_state() is a special case in the call graph and it has to be called for device X after we discover any devices *below* X.
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Remove lists from struct pcie_link_stateI don't think the "children" list is used at all, but it's possible I just don't understand the usage.

I don't understand how the "link" list works.

I think we should be able to do everything we need using the pci_bus->devices list and the pci_bus->parent links.
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Allocate pcie_link_state per device instead of per-linkWe currently allocate pcie_link_state only for the device at the upstream end of a link (see pcie_aspm_init_link_state()). This means we have to enumerate the downstream devices first before setting up ASPM data structures.

I think it would be better to allocate pcie_link_state for each end of the link, when we enumerate that device. We can't *enable* ASPM until we enumerate the downstream end, but we could allocate the structure and read the link capabilities earlier.
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Consider caching devcap, lnkcap in pci_devMaybe set_pcie_port_type() could read the capability registers (these are read-only)
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Consider getting rid of struct pcie_link_state by merging pieces into struct pci_dev (probably impractical)This would add overhead to pci_dev for conventional PCI (which obviously doesn't have links or ASPM) and for PCIe devices without links (e.g., integrated endpoints and VFs). It would be interesting to compare memory usage of pcie_link_state vs putting that info directly in pci_dev. Obviously there are fewer pcie_link_state structs than pci_devs (there's one for every link, so per *pair* of devices), but pcie_link_state has significant overhead that is redundant (pointers to pdev/downstream/root/parent, and sibling/children/link lists).

Maybe it would be better to just rework pcie_link_state so we allocate it for every device with a link instead of sharing one struct between the upstream and downstream ends of the link.
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Stop exporting pci_bus_semLooks like nothing outside drivers/pci/ uses it and (I think) no modules use it.
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Implement AER register values from ACPI HEST recordsSee ACPI v6.2, sec 18.3.2.4
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Add multi-domain support to Intel EDAChttps://lkml.kernel.org/r/20180808200747.GA219159@bhelgaas-glaptop.roam.corp.google.com
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Restructure EDAC drivers to use pci_register_driver()