LM5145_quickstart_calculator_A5.xlsm

	A	B	C	D	E	F	G	O	S
1	LM(2)5145/46-Q1 DC-DC Controller Design Tool
2
3	About		xx			= Input Box		TERMS OF USE
4
5	Step 1: Operating Specifications
6				Input Voltage ‒ Min, VIN(min)	8	V
7				Input Voltage ‒ Nom, VIN(nom)	48	V
8				Input Voltage ‒ Max, VIN(max)	75	V
9				Output Voltage, VOUT	5	V
10				Maximum Output Current, IOUT	8	A
11				Free-running Switching Frequency, FSW	300	kHz
12				SYNC Frequency (if used), FSW-SYNC	300	kHz
13				Frequency Set Resistor, RRT	33.2	kΩ
14
15	Step 2: Filter Inductor
16				Recommended Filter Inductance	5.6	µH
17				Inductance, LF	5.6	µH
18				Inductor DCR	10.2	mΩ
19				Pk-to-Pk Ripple Current at VIN(nom), DIL	2.8	APK-PK
20				Inductor Ripple Current as a % of Max IOUT	34	%
21				Estimate Core Loss at VIN(nom)	0.4	W
22
23	Step 3: RDS(on) or Shunt-Based Current Limit
24				Shunt, RS	6	mΩ			\
25				Required Current Limit Setpoint	12	A
26				Current Limit Set Resistor, RILIM	576	Ω
27				Min Inductor Sat Current, IL(SAT)	15.6	A
28				Power Loss in RS at Full Load, Max VIN	0.33	W
29
30	Step 4: Output Capacitance
31				Output Voltage Ripple Specification	100	mVPK-PK
32				Minimum Ideal Output Capacitance	11	µF
33				Total Output Capacitance (Derated), COUT	440	µF
34				Maximum Permitted ESR	36	mΩ
35				Output Capacitor ESR	1	mΩ
36				Resulting Output Voltage Ripple	4	mVPK-PK
37				Output Capacitor Ripple Current	0.8	ARMS
38
39	Step 5: Input Capacitance
40				Input Voltage Ripple Specification	500	mVPK-PK
41				Minimum Ideal Input Capacitance	5	µF
42				Total Input Capacitance (Derated), CIN	60	µF
43				Maximum Permitted ESR	49	mΩ
44				Input Capacitor ESR	0.66	mΩ
45				Resulting Input Voltage Ripple	49	mVPK-PK
46				Input Capacitor Ripple Current	2.5	ARMS
47
48	Step 6: Soft-start, UVLO
49				Soft-Start Time, tSS	4	ms
50				Soft-Start Capacitance, CSS	47	nF
51				Input Voltage UVLO Turn-On	8	V
52				Input Voltage UVLO Turn-Off	7	V
53				UVLO Upper Resistor, RUV1	100	kΩ
54				UVLO Lower Resistor, RUV2	17.8	kΩ
55	If the SYNC feature is not required, connect SYNCIN to GND
56	or VCC for DCM or CCM operation, respectively
57
58	Step 7: Compensation Design
59				LC Complex Pole Frequency	3.2	kHz
60				ESR Zero Frequency	362	kHz
61				Desired Crossover Frequency	30	kHz
62				Appropriate Midband Gain	0.62	V/V
63				Upper Feedback Resistor, RFB1	22.1	kΩ
64				Lower Feedback Resistor, RFB2	4.22	kΩ
65				Actual Output Voltage, VOUT	4.990	V
66
67	Pole & Zero Placement			FZ1	2.3	kHz
68	Baseline P/Z Frequencies:			FZ2	2.9	kHz
69				FP1	362	kHz
70				FP2	150	kHz
71
72	Compensation Components
73		Calculated /	Std Values	Selected		Actual P/Z Frequencies
74	RC1	13.7	13.7	13.7	kΩ	2.5	kHz (FZ1)
75	CC1	5144	4700	4700	pF	2.6	kHz (FZ2)
76	CC2	79	82	82	pF	331	kHz (FP1)
77	RC2	179	178	178	Ω	144	kHz (FP2)
78	CC3	2458	2700	2700	pF
79
80	Efficiency / Power Loss Analyzer
81
82	Step 8: Efficiency
83
84				High-Side MOSFET (Q1) Specifications	IAUZ30N10S5L240ATMA1
85				On-State Resistance, RDS(on)	19.5	mΩ
86				Total Gate Charge, QG	9.4	nC
87				Gate-Drain Charge, QGD	1.9	nC
88				Gate-Source Charge, QGS	2.7	nC
89				Output Capacitance, COSS	113	pF
90				Gate Resistance, RG	1.5	Ω
91				Transconductance, gFS	100	S
92				Gate-Source Plateau Voltage, VGS(MP)	3.3	V
93				Body Diode Forward Voltage, VBD1	0.9	V
94				Thermal Resistance, θJA	50	°C/W
95
96				Low-Side MOSFET (Q2) Specifications	IAUZ30N10S5L240ATMA1
97				On-State Resistance, RDS(on)	10.8	mΩ
98				Total Gate Charge, QG	17	nC
99				Output Charge, QOSS	30	nC
100				Output Capacitance, COSS	197	pF