ABCDEFGHIJKL
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NameDescriptionModel StructureModeled RXActual CAD RXRX DiscrepancyModeled CXActual CXCX Discrepancy
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NotesContactsSheetsContactsSheetsSheetSheet
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All Periphery FETsmXXXX d g s b w l m ad as pd ps nrd nrsnonediff(min)licon/mcon/viasdiff(ext)/poly/li/m1/m2-m3nonepoly/licon/lili/m1/m2-m3li-negligible
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20V NDEFETs NONISOxXXXX d g s b w l m ad as pd ps nrd nrsnonediff(min)/liconmcon/viasdiff(ext)/poly/li/m1/m2-m3nonepoly/licon/lili/m1/m2-m3li-negligible
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20V NDEFETs ISOxXXXX d g s b w l m ad as pd ps nrd nrsnonediff(min)/liconmcon/viasdiff(ext)/poly/li/m1/m2-m3nonepoly/licon/li/sky130_fd_pr__model__parasitic__diode_ps2dnli/m1/m2-m3li-negligible
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20V PDEFETsxXXXX d g s b w l m ad as pd ps nrd nrsnonediff(min)/liconmcon/viasdiff(ext)/poly/li/m1/m2-m3nonepoly/licon/lili/m1/m2-m3/sky130_fd_pr__model__parasitic__diode_ps2dn__hvli-negligible
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Cell FETsNOT EXTRACTED FROM LAYOUTN/AN/AN/AN/AN/AN/AN/AN/A
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All DiodesdXXXX n1 n2 area pjlicondifflicon/mcon/viaspoly/li/m1/m2-m3licon-negligibleJunctionli/m1/m2-m3none
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RF ESD Diodesxesd_XXXX n1 n2 area pjlicon/mcon/viali/m1/m2via2m3noneli/m1/m2m3none
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pnp_05v5Parasitic PNPqXXXX nc nb ne ns sky130_fd_pr__pnp_05v5_W0p68L0p68 mlicon/mcondiff/limcon/viasli/m1/m2-m3li/mcon-negliblenali/m1/m2-m3none
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Parasitic PNP (5X)qXXXX nc nb ne ns sky130_fd_pr__pnp_05v5_W3p40L3p40 mlicon/mcondiff/limcon/viasli/m1/m2-m3li/mcon-negliblenali/m1/m2-m3none
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npn_05v0Parasitic NPNqXXXX nc nb ne ns sky130_fd_pr__npn_05v5 mlicon/mcondiff/limcon/viasli/m1/m2-m3li/mcon-negliblenali/m1/m2-m3none
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res_generic_XXXNon-precision ResistorsrXXXX a b l w mnonesheet layerlicon/mcon/viasnone
(no sheet resistance where sheet layer & res id layer intersect)
nonenonejunction/li/m1/m2-m3parasitic capacitance to substrate (tool limitation)
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res_iso_pwIsolated Pwell ResistorxXXXX pwres r0 r1 b l w mlicon/mconpwell/liviasm1/m2-m3nonenonejunction/m1/m2-m3li-negligible
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res_high_XXXPrecision poly resistorxXXXXX hrpoly_X_X r0 r1 b l w mlicon/mconpoly/liviam1/m2-m3nonepoly-subm1/m2-m3li-negligible
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cap_mim_XXXXMIM Capacitor (2-terminal)xXXXX sky130_fd_pr__cap_mim_m3_2 c0 c1 w l mvia2m3N/Apoly/li/m1/m2m2 (of the device) -negligiblecapm-m2li/m1/m2-m3routing layers underneath device
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cap_mim_XXXXMIM Capacitor (3-terminal)xXXXX sky130_fd_pr__model__cap_mim c0 c1 b w l mvia2m3N/Apoly/li/m1/m2m2 (of the device) -negligiblem2-sub/capm-m2(1) Carea of M2-sub (non-overlap CAPM w/ 0.14um upsize)
(2) M3 Cap by 1 snap grid width
none
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cap_vpp_XXXXVertical Parallel Plate CapxXXXX sky130_fd_pr__cap_vpp_XXXXX c0 c1 b mNo special RCX implementation for VPP required since black-box LVS will be usedmcon/viali/m1/m2none
(black box LVS)
none
(black box LVS)
noneli/mcon//m1/via/m2none (black box LVS)Parasitic capacitance to routing above
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cap_vpp_XXXXVertical Parallel Plate Cap over MOSCAPxXXXX sky130_fd_pr__cap_vpp_XXXXX c0 c1 b mmcon/viali/m1/m2none
(black box LVS)
none
(black box LVS)
noneli/mcon//m1/via/m2none (black box LVS)Parasitic capacitance to routing above
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cap_vpp_XXXX4-terminal Vertical Parallel Plate Cap
(M3 Shielded)
xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b term4 m=licon/mcon/viapoly/li/m1/m2via3/via4m3/m4/m5nonepoly/licon/li/mcon/m1/via/m2/m3m3-substrate (not m3-m2), neighboring metal to VPP metalnone
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cap_vpp_XXXX4-terminal Vertical Parallel Plate Cap
(M5 Shielded)
xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b term4 m=licon/mcon/via/via2/via3poly/li/m1/m2/m3/m4via4m5nonepoly/licon/li/mcon/m1/via/m2/m3/m4/m5neighboring metal to VPP metalnone
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cap_vpp_XXXX3-terminal Vertical Parallel Plate CapxXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m=
xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m=
mcon/viali/m1/m2via2/via3/via4m3/m4/m5noneli/mcon/m1/via/m2neighboring metal to VPP metalParasitic capacitance to routing above
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cap_vpp_XXXX3-terminal Vertical Parallel Plate CapxXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m=mcon/via/via2li/m1/m2/m3via3/via4m4/m5noneli/mcon/m1/via/m2/via2/m3neighboring metal to VPP metalnone
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cap_var_XXXXVaractorxXXXXX sky130_fd_pr__cap_var_XXXX c0 c1 b l w mlicon/mcon/viadiff/poly/li/m1/m2via2m3nonepoly/li/m1/m2nwdiodemodel/m3*none
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InductorxXXXXX xindXXXX t1 t2 bodyNo special RCX implementation for inductor required since black-box LVS will be usedviam2/CuNothing extracted within inductor.dg layernonem2/via/CuNothing extracted within inductor.dg layernone