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CommenttCWL: Depends on frequency, see data sheet and conditional formattingtCK: See conditional format for limits depending on CLtCWL(min) is a guess. Elpida's data sheet only specifies min CWL in clocks=RL+tCCD/2+2nCK-WL where RL=AL+CL (assume AL=0), WL=CL
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Datasheet min ns/CLK]44451604443.91.0712.8412.8412.84347.557.59.51546.847.544
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Datasheet max [ns/CLK]99999999999999997.83.33320999999999999999999999999
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[Asus BIOS] NameCAS# LatencyRAS# to CAS# DelayRAS# PRE TimeRAS# ACT TimeREAD to PRE TimeRAS# to RAS# DelayWRITE to READ delayCAS# write LatencyWRITE Recovery TimeREF Cycle TimeRow Cycle TimeREAD to WRITE DelayWRITE to READ Delay (DD)WRITE to WRITE TimingREAD to READ TimingRefresh RateCommand RateUnder Prime95Memtest86+ 4.2
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Vf [MHz]tCAS [CLK]tRCD [CLK]tRP [CLK]tRAS [CLK]tRTP [CLK]tRRD [CLK]tWTR [CLK]tCWL [CLK]tWR [CLK]tRFC [ns]tRC [CLK]tRTW [CLK]tWTR [CLK]tWW [CLK]tRR [CLK]tREF [us]Command Rate [CLK]DRAM Driving ControlDIMM0 Temp [C]DIMM1 Temp [C]DIMM2 Temp [C]DIMM3 Temp [C]fCPU [MHz]L1 [MB]sL2 [MB/2]L3 [MB/s]Memory [MB/s]Theor. Peak Data rate [MB/s]tCK [ns]tAA or tCL [ns]tRCD [ns]tRP [ns]tRAS [ns]tRTP [ns]tRRD [ns]tWTR [ns]tCWL [ns]tWR [ns]tRC [ns]tRTW [ns]tRTWmin [ns]tWTR [ns]tCCD(WW) [ns]tCCD(RR) [ns]
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baseline1.35106699924444681602781457.823612708262822010592735685281.87617260816.8855534716.8855534716.8855534745.028142597.5046904327.5046904327.50469043211.2570356515.0093808650.6566604115.009380868.4427767351.8761726087.5046904329.380863039
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Stock1.251333999245447101603391457.824244434436127082628220105928831106641.50037509413.5033758413.5033758413.5033758436.009002257.5018754696.0015003756.00150037510.5026256615.0037509449.5123780913.503375846.7516879221.5003750946.0015003757.501875469
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fast1.351866101211286668143004696667.823233333242148263332924116739365149281.07181136110.7181136112.8617363311.7899249730.010718116.4308681676.4308681676.4308681678.5744908915.0053590649.303322629.6463022515.3590568066.4308681676.4308681676.430868167
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RAM