AM4 Pinout Diagram & Look up table

	A	B	C	D	E	F	G	H	I	J	K	L	M	N	O	P	Q	R	S	T	U	V	W	X	Y	Z	AA	AB	AC	AD	AE	AF	AG	AH	AI	AJ	AK	AL	AM
1	vd								Reddit: imskripted

2			VSS	P_GFX_TXP[0]	P_GFX_TXN[0]	VSS	P_GFX_TXP[3]	P_GFX_TXN[3]	VSS	P_GFX_TXP[6]	P_GFX_TXN[6]	VSS	P_GFX_TXP[9]	P_GFX_TXN[9]	VSS	P_GFX_TXP[12]	P_GFX_TXN[12]	VSS	P_GFX_TXP[15]	P_GFX_TXN[15]	VSS	USB_SS_1TXP	USB_SS_1TXN	VSS	USB_SS_3RXP	USB_SS_3RXN	VSS	X48M_X2	X48M_X1	VSS	USB_OC0_L/AGPIO16	USB_OC1_L/TDI/AGPIO17	VSS	USB_OC3_L/TDO/AGPIO24	USB_OC2_L/TCK/AGPIO18	VSS	AZ_RST_L
3			DP0_TXN[0]	DP0_TXP[0]	VDDCR_SOC	P_GFX_TXP[2]	P_GFX_TXN[2]	VDDCR_SOC	P_GFX_TXP[5]	P_GFX_TXN[5]	VDDCR_SOC	P_GFX_TXP[8]	P_GFX_TXN[8]	VDDCR_CPU	P_GFX_TXP[11]	P_GFX_TXN[11]	VDDCR_CPU	P_GFX_TXP[14]	P_GFX_TXN[14]	VDDCR_CPU	USB_SS_1RXP	RSVD	VDDCR_CPU	USB_SS_2RXP	USB_SS_2RXN	VDDCR_CPU	USB_SS_3TXP	RSVD	VDDCR_CPU	SDA1/I2C3_SDA/AGPIO20	LPC_PME_L/AGPIO22	VDDCR_CPU	AGPIO9/SGPIO0_DATAOUT	SLP_S5_L	VDDCR_CPU	SLP_S3_L	AZ_SYNC	VSS
4	VSS	DP0_TXN[1]	DP0_TXP[1]	VDDCR_SOC	P_GFX_TXP[1]	P_GFX_TXN[1]	VDDCR_SOC	P_GFX_TXP[4]	P_GFX_TXN[4]	VDDCR_SOC	P_GFX_TXP[7]	P_GFX_TXN[7]	VDDCR_CPU	P_GFX_TXP[10]	P_GFX_TXN[10]	VDDCR_CPU	P_GFX_TXP[13]	P_GFX_TXN[13]	VDDCR_CPU	USB_SS_0RXP	USB_SS_1RXN	VDDCR_CPU	USB_SS_2TXP	RSVD	VDDCR_CPU	USB_SS_0TXP	USB_SS_3TXN	VDDCR_CPU	USB0_ZVSS	SCL1/I2C3_SCL/AGPIO19	VDDCR_CPU	PWR_GOOD	AGPIO23/SGPIO0_LOAD	VDDCR_CPU	S0A3_GPIO/AGPIO10/SGPIO0_CLK	TEST2	VDDCR_CPU	AZ_SDIN0	AZ_BITCLK
5	DP0_TXN[2]	DP0_TXP[2]	VDDCR_SOC	DP1_TXP[0]	VSS	VSS	P_GFX_RXN[1]	VSS	VSS	P_GFX_RXN[5]	VSS	VSS	P_GFX_RXN[9]	VSS	VSS	P_GFX_RXP[13]	VSS	VSS	P_HUB_RXP[3]	USB_SS_0RXN	VSS	TEST10	USB_SS_2TXN	VSS	P_HUB_TXP[0]	USB_SS_0TXN	VSS	GPP_CLK1P	USB_SS_ZVSS	VSS	TEST46[13]	SYS_RESET_L/AGPIO1	VSS	S5_MUX_CTRL/EGPIO42	AGPIO40/SGPIO0_DATAIN	VDDCR_CPU	AZ_SDOUT	AZ_SDIN2	VSS
6	RSVD	VDDCR_SOC	DP0_TXP[3]	DP1_TXN[0]	VSS	P_GFX_RXN[0]	P_GFX_RXP[1]	VSS	P_GFX_RXN[3]	P_GFX_RXP[5]	VSS	P_GFX_RXN[7]	P_GFX_RXP[9]	VSS	P_GFX_RXN[11]	P_GFX_RXN[13]	VSS	P_GFX_RXN[15]	P_HUB_RXN[3]	VSS	P_HUB_TXP[1]	P_HUB_TXN[1]	VSS	P_HUB_TXP[3]	P_HUB_TXN[0]	VSS	GPP_CLK0P	GPP_CLK1N	VSS	USB3_ZVSS	WAKE_L/AGPIO2	VSS	PWR_BTN_L/AGPIO0	RSMRST_L	VSS	BLINK/AGPIO11	AZ_SDIN1	VDDCR_CPU	X32K_X1
7	VSS	DP2_TXP[0]	DP0_TXN[3]	VSS	TEST28_H	P_GFX_RXP[0]	VDDCR_SOC	P_GFX_RXN[2]	P_GFX_RXP[3]	VDDCR_SOC	P_GFX_RXN[6]	P_GFX_RXP[7]	VDDCR_CPU	P_GFX_RXN[10]	P_GFX_RXP[11]	VDDCR_CPU	P_GFX_RXN[14]	P_GFX_RXP[15]	VDDCR_CPU	P_HUB_RXP[2]	VSS	VDDCR_CPU	P_HUB_TXP[2]	P_HUB_TXN[3]	VDDCR_CPU	GFX_CLKP	GPP_CLK0N	VDDCR_CPU	GPP_CLK3P	USB2_ZVSS	VDDCR_CPU	TEST0	USB1_ZVSS	VSS	AGPIO4	AGPIO3	VDDCR_CPU	SATA_ZVSS	X32K_X2
8	DP2_TXP[1]	DP2_TXN[0]	VDDCR_SOC	DP1_TXP[1]	TEST28_L	VDDCR_SOC	VSS	P_GFX_RXP[2]	VDDCR_SOC	P_GFX_RXN[4]	P_GFX_RXP[6]	VDDCR_CPU	P_GFX_RXN[8]	P_GFX_RXP[10]	VDDCR_CPU	P_GFX_RXN[12]	P_GFX_RXP[14]	VSS	P_ZVSS	P_HUB_RXN[2]	VDDCR_CPU	VSS	P_HUB_TXN[2]	VDDCR_CPU	VSS	GFX_CLKN	VDDCR_CPU	GPP_CLK2P	GPP_CLK3N	VDDCR_CPU	PCIE_RST_L/EGPIO26	TEST1/TMS	VDDCR_CPU	AGPIO8	48M_OSC	VSS	USB_HSD0P	SATA_ZVDDP	VSS
9	DP2_TXN[1]	VDDCR_SOC	DP2_TXP[2]	DP1_TXN[1]	VSS	DP1_TXP[2]	DP1_TXN[2]	VSS	VSS	P_GFX_RXP[4]	VSS	VSS	P_GFX_RXP[8]	VSS	VSS	P_GFX_RXP[12]	VSS	P0A_ZVSS	P_ZVDDP	VSS	P_HUB_RXN[1]	P_HUB_RXP[1]	VSS	P_HUB_RXN[0]	P_HUB_RXP[0]	VSS	VSS	GPP_CLK2N	VSS	USB_SS_ZVDDP	AM4R1	VDDCR_CPU	AGPIO6	RTCCLK	VSS	P0B_ZVSS	USB_HSD0N	VDDCR_CPU	USB_HSD1P
10	VSS	DP2_TXP[3]	DP2_TXN[2]	VSS	DP1_TXP[3]	DP1_TXN[3]	VDDCR_SOC	DP0_HPD	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	P_GPP_RXP[1]	CORETYPE[1]	VDDCR_CPU	P_GPP_RXP[0]	P_GPP_RXN[0]	VDDCR_CPU	USB_HSD3P	USB_HSD1N
11	DP2_AUXP	DP2_TXN[3]	VDDCR_SOC	DP1_HPD	DP2_HPD	VDDCR_SOC	DP0_AUXP	DP0_AUXN	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	P_GPP_RXN[1]	VDDCR_CPU	P_GPP_RXN[2]/SATA_RX0N	P_GPP_RXP[2]/SATA_RX0P	VSS	USB_HSD2P	USB_HSD3N	VSS
12	DP2_AUXN	VDDCR_SOC	TEST16	TEST17	VSS	DP1_AUXP	DP1_AUXN	VSS	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VSS	P_GPP_RXN[3]/SATA_RX1N	P_GPP_RXP[3]/SATA_RX1P	VSS	USB_ZVSS	USB_HSD2N	VDDCR_CPU	EGPIO95
13	VSS	TEST15	TEST14	VSS	DP_AUX_ZVSS	DP_ZVSS	VDDCR_SOC	DP_VARY_BL	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	RSVD	RSVD	VDDCR_CPU	P_GPP_TXN[0]	P_GPP_TXP[0]	VDDCR_CPU	EGPIO96	EGPIO97
14	TEST11	TRST_L	VDDCR_SOC	TEST6	DBRDY	VDDCR_SOC	DP_BLON	DP_DIGON	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	P_GPP_TXP[2]/SATA_TX0P	P_GPP_TXN[2]/SATA_TX0N	VDDCR_CPU	P_GPP_TXP[1]	P_GPP_TXN[1]	VSS	EGPIO98	EGPIO99	VSS
15	TDI	VDDCR_SOC	TDO	DBREQ_L	VSS	VDDCR_CPU_SENSE	VDDIO_MEM_S3_SENSE	VSS	VDDCR_SOC	DP_STEREOSYNC	VDDCR_SOC	VSS	VDDCR_SOC														VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDCR_CPU	VSS	P_GPP_TXP[3]/SATA_TX1P	P_GPP_TXN[3]/SATA_TX1N	VSS	EGPIO100	SPI_DI/ESPI_DAT1/EGPIO120	VDDCR_CPU	SPI_CLK/ESPI_CLK/EGPIO117
16	VSS	TMS	TCK	VSS	VDDCR_SOC_SENSE	VSS_SENSE_A	VDDCR_SOC	PROCHOT_L	VSS	VDDCR_SOC	VSS	VDDCR_SOC	VSS														VSS	VDDCR_CPU	VDD_18_S5	VDD_18_S5	VDDBT_RTC_G	VDDIO_AUDIO	RSVD	RSVD	RSVD	ESPI_ALERT_L/LDRQ0_L/EGPIO108	VDDCR_CPU	SPI_HOLD_L/ESPI_DAT3/EGPIO133	SPI_CS2_L/ESPI_CS_L/EGPIO119
17	TEST41	RESET_L	VDDCR_SOC	ALERT_L	PWROK	VDDCR_SOC	TEST18	TEST19	VDDCR_SOC		VDDCR_SOC	VSS	VDDCR_SOC														VDDCR_CPU	VSS	VDDP_S5		RSVD	RSVD	RSVD	RSVD	RSVD	VSS	SPI_DO/ESPI_DAT0/EGPIO121	SPI_WP_L/ESPI_DAT2/EGPIO122	VSS
18	SVT	VDDCR_SOC	SVD	SVC	VSS	VSS	RSVD	VSS	VSS		VSS	VDDCR_SOC	VSS														VSS	VDDCR_CPU	VDDP_S5		RSVD	RSVD	RSVD	RSVD	VSS	SPI_CS1_L/EGPIO118	SPI_TPM_CS_L/AGPIO76	VSS	AGPIO86
19	VSS	SIC	SID	VSS	MA_DATA[0]	MA_DATA[5]	VDDCR_SOC	MA_DATA[4]	MA_DATA[1]	VSS	VDDCR_SOC	VSS	VDDCR_SOC														VDDCR_CPU	VSS	VDDCR_SOC_S5	VDDCR_SOC_S5	RSVD	VDDP	VDDP	VDDP	RSVD	EGPIO70	VSS	LPC_PD_L/AGPIO21	LFRAME_L/EGPIO109
20	THERMTRIP_L	VSS	VDDCR_SOC	VSS	RSVD	VSS	MA_DQS_L[0]	MA_DQS_H[0]	VSS	MA_DM[0]	VSS	VDDCR_SOC	VSS														VSS	VDDCR_CPU	VDD_33_S5	VDD_33_S5	RSVD	VDDP	VDDP	VDDP	RSVD	RSVD	LPCCLK1/EGPIO75	LPC_CLKRUN_L/AGPIO88	VSS
21	MB_DATA[4]	VDDCR_SOC	MB_DATA[5]	MB_DATA[0]	VSS	MA_DATA[7]	MA_DATA[6]	VSS	MA_DATA[2]	VSS	VDDCR_SOC	VSS	VDDCR_SOC														VDDCR_CPU	VSS	VDD_18	VDD_18	RSVD	VDDP	VDDP	VDDP	RSVD	LAD3/EGPIO107	LPCCLK0/EGPIO74	VSS	LAD0/EGPIO104
22	VSS	MB_DATA[1]	MB_DM[0]	VSS	VSS	MA_DATA[12]	VSS	MA_DATA[3]	MA_DATA[13]	VSS	VSS	VDDCR_SOC	VSS														VSS	VDDCR_CPU	VDD_33	VDD_33	RSVD	RSVD	RSVD	RSVD	RSVD	LAD2/EGPIO106	VSS	LAD1/EGPIO105	SERIRQ/AGPIO87
23	MB_DQS_L[0]	MB_DQS_H[0]	VSS	VSS	RSVD	VSS	MA_DATA[9]	MA_DATA[8]	VSS	VSS	VDDCR_SOC	TEST5	VDDCR_SOC														VDDCR_CPU	VSS	VDDCR_CPU	VSS	VDDP_SENSE	SATA_ACT_L/AGPIO130	VSS	AGPIO5/DEVSLP0	CLK_REQG_L/OSCIN/EGPIO132	VSS	LPC_RST_L	GENINT1_L/AGPIO89	VSS
24	MB_DATA[6]	VSS	MB_DATA[7]	VSS	VSS	MA_DQS_H[1]	MA_DQS_L[1]	VSS	MA_DM[1]	VSS	TEST4	VDDCR_SOC	VSS														VSS	VDDCR_CPU	VSS		CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131	VSS_SENSE_B	FANIN0/AGPIO84	FANOUT0/AGPIO85	VSS	CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92	GENINT2_L/AGPIO90	VSS	SPKR/AGPIO91
25	VSS	MB_DATA[2]	MB_DATA[3]	VSS	MA_DATA[10]	MA_DATA[15]	VSS	MA_DATA[14]	MA_DATA[11]		VDDCR_SOC	VSS	VDDCR_SOC														VDDCR_CPU	VSS	VDDCR_CPU		VSS	CORETYPE[0]	ESPI_RESET_L/KBRST_L	VSS	RSVD	CLK_REQ2_L/AGPIO116	VSS	CLK_REQ1_L/AGPIO115	RSVD
26	MB_DATA[12]	MB_DATA[13]	VSS	VSS	RSVD	VSS	MA_DATA[21]	MA_DATA[20]	VSS		VSS	VDDCR_SOC	VSS														VSS	VDDCR_CPU	VSS	VSS	MA_DATA[62]	MA_DATA[63]	VSS	MA_DATA[58]	MA_DATA[59]	RSVD	SCL0/I2C2_SCL/EGPIO113	SDA0/I2C2_SDA/EGPIO114	VSS
27	MB_DATA[8]	VSS	MB_DATA[9]	MB_DM[1]	VSS	MA_DQS_L[2]	MA_DM[2]	VSS	MA_DATA[16]	VSS	VDDCR_SOC	VSS	VDDCR_SOC														VDDCR_CPU	VSS	VSS	MA_DATA[57]	MA_DM[7]	VSS	MA_DQS_L[7]	MA_DQS_H[7]	VSS	VSS	VSS	VSS	MB_DATA[59]
28	VSS	MB_DQS_L[1]	MB_DQS_H[1]	VSS	VSS	MA_DQS_H[2]	VSS	MA_DATA[23]	MA_DATA[17]	VSS	VSS	VSS	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDCR_CPU	VSS	MA_DATA[56]	VSS	MA_DATA[61]	MA_DATA[60]	VSS	VSS	VSS	VSS	MB_DATA[63]	MB_DATA[58]
29	MB_DATA[14]	MB_DATA[15]	VSS	RSVD	MA_DATA[22]	VSS	MA_DATA[18]	MA_DATA[19]	VSS	VSS	VSS	VSS	VDDIO_MEM_S3	TEST47	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VSS	VSS	VSS	VSS	MA_DATA[51]	MA_DATA[50]	VSS	MA_DATA[54]	MA_DATA[55]	VSS	MB_DQS_H[7]	MB_DATA[62]	VSS
30	MB_DATA[10]	VSS	MB_DATA[11]	VSS	VSS	MA_DATA[24]	MA_DATA[29]	VSS	MA_DATA[28]	VSS	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VSS	VSS	MA_DATA[49]	MA_DM[6]	VSS	MA_DQS_L[6]	MA_DQS_H[6]	VSS	VSS	MB_DQS_L[7]	VSS	MB_DM[7]
31	VSS	MB_DATA[20]	MB_DATA[21]	VSS	MA_DQS_L[3]	MA_DQS_H[3]	VSS	MA_DM[3]	MA_DATA[25]	VSS	VSS	MA0_CKE[1]	VDDIO_MEM_S3	MA_ADD[8]	MA_ADD[4]	VSS	VDDIO_MEM_S3	VSS	TEST40	VSS	TEST31	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VSS	VSS	MA_DATA[33]	MA_DATA[34]	VSS	MA_DATA[52]	MA_DATA[53]	VSS	VSS	RSVD	VSS	MB_DATA[57]	MB_DATA[56]
32	MB_DATA[16]	MB_DATA[17]	VSS	VSS	MA_DATA[30]	VSS	MA_DATA[31]	MA_DATA[26]	VSS	MA_CHECK[2]	VSS	VDDIO_MEM_S3	MA_BG[0]	MA_ADD[9]	VDDIO_MEM_S3	MA_ADD[3]	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	VDDIO_MEM_S3	VSS	MA0_ODT[1]	VSS	MA_DATA[36]	MA_DM[4]	VSS	MA_DATA[45]	MA_DM[5]	VSS	MA_DATA[42]	MA_DATA[48]	VSS	MB_DATA[61]	MB_DATA[60]	VSS
33	MB_DM[2]	VSS	MB_DQS_L[2]	VSS	VSS	MA_DATA[27]	MA_CHECK[1]	VSS	MA_CHECK[6]	MA_CHECK[3]	VDDIO_MEM_S3	MA0_CKE[0]	MA_BG[1]	VDDIO_MEM_S3	MA_ADD[6]	MA_ADD[1]	VDDIO_MEM_S3	MA_CLK_H[3]	MA_CLK_L[3]	VDDIO_MEM_S3	MA_ADD[0]	VDDIO_MEM_S3	VDDIO_MEM_S3	MA_CAS_L_ADD[15]	MA_ADD[13]	VDDIO_MEM_S3	VSS	MA_DATA[37]	VSS	MA_DATA[39]	MA_DATA[44]	VSS	MA_DQS_H[5]	MA_DATA[47]	VSS	VSS	MB_DATA[51]	VSS	MB_DATA[50]
34	VSS	MB_DATA[22]	MB_DQS_H[2]	VSS	MA_CHECK[4]	MA_CHECK[0]	VSS	MA_DQS_L[8]	MA_CHECK[7]	VSS	MA_RESET_L	MA1_CKE[0]	VDDIO_MEM_S3	MA_ADD[11]	MA_ADD[5]	VDDIO_MEM_S3	MA_CLK_H[1]	MA_CLK_L[1]	VDDIO_MEM_S3	MA_PAROUT	MA_BANK[1]	VDDIO_MEM_S3	MA0_CS_L[0]	MA1_ODT[0]	VDDIO_MEM_S3	MA_ADD_17	VDDIO_MEM_S3	VSS	MA_DQS_H[4]	MA_DATA[38]	VSS	MA_DATA[41]	MA_DQS_L[5]	VSS	MA_DATA[43]	VSS	VSS	MB_DATA[55]	MB_DATA[54]
35	MB_DATA[23]	MB_DATA[18]	VSS	VSS	MA_CHECK[5]	VSS	MA_DM[8]	MA_DQS_H[8]	VSS	RSVD	MA1_CKE[1]	VDDIO_MEM_S3	MA_ALERT_L	MA_ADD[7]	VDDIO_MEM_S3	MA_CLK_H[0]	MA_CLK_L[0]	VDDIO_MEM_S3	VDDIO_MEM_S3	VDDIO_MEM_S3	VDDIO_MEM_S3	MA_RAS_L_ADD[16]	MA1_CS_L[0]	VDDIO_MEM_S3	MA1_CS_L[1]	MA1_ODT[1]	VDDIO_MEM_S3	MA_DATA[32]	MA_DQS_L[4]	RSVD	MA_DATA[35]	MA_DATA[40]	VSS	MA_DATA[46]	VSS	VSS	MB_DQS_H[6]	MB_DQS_L[6]	VSS
36	MB_DATA[28]	VSS	MB_DATA[19]	VSS	VSS	VSS	VSS	VSS	VSS	MB_RESET_L	VDDIO_MEM_S3	MA_ACT_L	MA_ADD[12]	VDDIO_MEM_S3	RSVD	MA_ADD[2]	VDDIO_MEM_S3	MA_CLK_H[2]	MA_EVENT_L	MB_ZVDDIO_MEM_S3	MA_BANK[0]	MA_WE_L_ADD[14]	VDDIO_MEM_S3	MA0_ODT[0]	MA0_CS_L[1]	VDDIO_MEM_S3	VDDIO_MEM_S3	RSVD	VSS	VSS	VSS	VSS	VSS	VSS	VSS	MB_DM[6]	MB_DATA[49]	VSS	MB_DATA[48]
37	VSS	MB_DATA[24]	MB_DATA[29]	VSS	MB_DATA[25]	MB_CHECK[1]	VSS	MB_CHECK[6]	RSVD	VDDIO_MEM_S3	MB1_CKE[1]	MB_BG[0]	VDDIO_MEM_S3	MB_ADD[9]	MB_ADD[6]	VDDIO_MEM_S3	MB_ADD[1]	MA_CLK_L[2]	VDDIO_MEM_S3	MB_CLK_L[2]	MA_ADD[10]	VDDIO_MEM_S3	MB_ADD[0]	MB_RAS_L_ADD[16]	VDDIO_MEM_S3	MB_CAS_L_ADD[15]	MB1_CS_L[1]	MB0_ODT[1]	VSS	MB_DATA[37]	VSS	MB_DQS_L[4]	MB_DATA[34]	VSS	MB_DATA[40]	MB_DATA[46]	VSS	MB_DATA[52]	MB_DATA[53]
38	MB_DQS_L[3]	MB_DQS_H[3]	VSS	MB_DM[3]	MB_CHECK[4]	VSS	MB_DQS_L[8]	MB_CHECK[7]	VSS	MB0_CKE[1]	MB0_CKE[0]	VDDIO_MEM_S3	MB_ALERT_L	MB_ADD[11]	VDDIO_MEM_S3	MB_ADD[4]	MB_ADD[2]	VDDIO_MEM_S3	MB_CLK_H[2]	VDDIO_MEM_S3	VDDIO_MEM_S3	RSVD	MB_BANK[1]	VDDIO_MEM_S3	MB0_CS_L[0]	MB1_ODT[0]	VDDIO_MEM_S3	MB_ADD_17	MA_ZVSS	VSS	MB_DATA[33]	MB_DQS_H[4]	VSS	MB_DATA[44]	MB_DATA[41]	VSS	MB_DATA[42]	MB_DATA[43]	VSS
39		MB_DATA[30]	MB_DATA[31]	MB_DATA[27]	VSS	MB_CHECK[0]	MB_DQS_H[8]	VSS	RSVD	RSVD	VDDIO_MEM_S3	MB_ACT_L	MB_ADD[12]	VDDIO_MEM_S3	MB_ADD[8]	MB_ADD[3]	VDDIO_MEM_S3	MB_CLK_H[1]	MB_CLK_L[1]	MB_CLK_H[3]	MB_EVENT_L	MB_PAROUT	VDDIO_MEM_S3	MB_BANK[0]	MB1_CS_L[0]	VDDIO_MEM_S3	MB_ADD[13]	MB1_ODT[1]	VSS	MB_DATA[36]	MB_DM[4]	VSS	MB_DATA[39]	MB_DATA[45]	VSS	MB_DQS_H[5]	MB_DATA[47]	VSS
40			MB_DATA[26]	VSS	MB_CHECK[5]	MB_DM[8]	VSS	MB_CHECK[2]	MB_CHECK[3]	VDDIO_MEM_S3	MB1_CKE[0]	MB_BG[1]	VDDIO_MEM_S3	MB_ADD[7]	MB_ADD[5]	VDDIO_MEM_S3	MB_CLK_H[0]	MB_CLK_L[0]	VDDIO_MEM_S3	MA_ZVDDIO_MEM_S3	MB_CLK_L[3]	VDDIO_MEM_S3	MB_ADD[10]	MB_WE_L_ADD[14]	VDDIO_MEM_S3	MB0_ODT[0]	MB0_CS_L[1]	VDDIO_MEM_S3	MB_ZVSS	MB_DATA[32]	VSS	MB_DATA[38]	MB_DATA[35]	VSS	MB_DM[5]	MB_DQS_L[5]	VSS
41
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44
45
46
47
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53
54
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