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Item Namedate of last changeCategoryPrimary GroupSecondary GroupSkill Set Concat Abbrevs bfrom below tablePriority (l/m/h)Effort (s/m/l/xl)When needed (CYQ)(projected) Start DateProjected End DateproposerOne line description
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OptimizerCompilersTool Chainmxlongoingmark himelsteincoordinate/share optimization efforts
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GCC code-qualityCompilersTool ChainSystematic coverage and code-quality improvements
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LTO supportCompilersTool ChainLink-time optimisation support is missing
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LLVMCompilersTool Chain
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performance analysisToolsTool Chain
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jemallocLibrariesSoftware
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OpenSSL optimisationsLibrariesSoftwarebitmanip, crypto, tuning
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ContainersToolsSoftware
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Javascript V8RuntimesSoftware
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Rust (LLVM-based)RuntimesSoftware
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golangRuntimesSoftware
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phpRuntimesSoftware
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pythonRuntimesSoftware
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JavaRuntimesSoftwaremlnxt yrKen DockserJRE: JVM, JIT
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optimize for SPEC2017 (SPEC2006)CompilersTool Chaincoordinate efforts for analysis and middle-end improvements (e.g. vectorisation)
similar coordination is happening for ARMv8
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mathLibrariesSoftwarelapack, eigen, ...
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OpenCVLibrariesSoftware
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virtual memory specSpecificationsvirtual memoryhmnowongoingdan lustigfinish spec
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virtual machinesplatformmmark himelsteinidentify work needed to use hypervisor spec by VMs, identify targets, manage efforts, get distro builds underway
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build/releaseInfrastructuresoftwaretool chainhmnowQ32020Q12021mark himelsteindraft distros to support base profiles
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lifecycleProcessTSCsoftwarehlnowQ32020Q12021mark himelsteinbase profiles/uefi/devicet tree choices for distros, custom profiles & app comatibility, EOL, versioning/naming
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docsTSCmmnowQ42020ongoingallediting, polishing existing and new specs, integrate Sail spec, cross- spec glossary and index
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better calendarInfrastructureTSChsnowQ32020Q32020allstephano&jeffro to implement
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complete & maintain sailGolden ModelFormal SpechlnowQ32020ongoingrichard newell, et. aladd new changes, extensions, formal model generation, maintain, refactor, compare with written spec, find and fix bugs
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security response teamSecuritySecurityhsnowQ42020
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cache manage operationsISAPrivileged ISAhmnowTariq Kurdcache flush/invalidate, prefetch, TLB invalidate. Andy Glew has a proposal
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extension to reduce code sizeISAnew TGhlnowTariq Kurdneed to be competitive on code size for embedded cores, now often 15% larger
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evaluation/development hardware for OSS developersInfrastructure
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compatibility tests for legacy v1.11 priv specTGPrivileged ISAACThhnowneeds rsrcAllen Baumneed M,S tests w/ good coverage, defined coverage, testing all features, ISA TG in email mode
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RV32D SAIL supportTGunPrivileged ISAACThmnowQ2-2021Q4-2021Allen Baumsupport is missing entirely from SAIL
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compatibility tests for legacy F/D specsTGunPrivileged ISAACThmnowQ2-2021Q4-2021Allen Baumneed F,D tests w/ good coverage, defined coverage, testing all features
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compatibility tests for legacy A-ext specsTGunPrivileged ISAACThmnowneeds rsrcAllen Baumneed A-ext tests w/ good coverage, defined coverage, testing all features
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profile comparison toolToolsACTSW profilelsEOYneeds rsrcAllen Baumdetermines whether a device profile meets platform profile requirements
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multi-mode interrupt handlerTGACTInfrastructure HChmEOYneeds rsrcAllen Baumreplicate interrupt handler for each possible mode: M, VS,S
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compatibility tests for non-determinismTGACTPrivmh?needs rsrcAllen Baumwe need test infrastructure that can test for non-architectural state dependent results (assume some some small fixed number of different results)
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hardening test macrosTGACTInfrastructure HCmh?needs rsrcAllen Baumensure macros don't break when constants exceed immediate op sizes
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Reducing compatibility test size - out-of-line assertionsACTTSCllEOYQ3-2022EOYAllen Baummove assertion code to be out-of-line to reduce test sizes
Now part of ACT policy and Branding policy - ACT under review
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compatibility tests for concurrencyTGACTFormal, MemModel, +?lhnxt yearneeds rsrcAllen Baumwe don't know how to test anything timing or ordering dependent (mem model, interrupts)Some of this requires new framework. ABI for event generators (interrupts,memory writes) being defined, but implementation is currently envisioned as vendor /model specific
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config. dependent reference modelTGACTPriv, UnprivhmnowEOY21ongoingAllen BaumFormal model needs to be configurable for WARL fields and optional behaviorWARL configuration of Sail in progress
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compatibility tests dependency on ratified spec (legacy)TGACTPriv, Unprivhmnowneeds rsrcAllen BaumNew extensions are held back by missing tests of ratified spec
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instruction encoding allocationISAUnprivPrivhmyesterdayneeds rsrcKen DockserSubgroup needed to oversee opcode/instruction encoding allocation
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compatibility test testplansISAACTUnprivhl
yesterday
Ken DockserDetailed plan of what needs to be tested for each of the instructions; need for contractors to provide what we needShould be the responsibility of the TGs creating instruction or feature
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Process for certifying passing arch testsProcessACTTSCmlEOYQ3-2021EOYAllen BaumDefine process for apply for trademark: beside passing architecture tests, what is needed to apply for a license? A report containing what, sent to whom?
Now part of ACT policy and Branding policy - ACT under review
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Certifying HW and RTLProcessACT, BrandingTSCmlEOYQ4-2020EOYAllen BaumDefine the process for HW based on licensed cores that are licensed to use the trademarks to be allowed themselves be licensed to use the trademarksPart of Branding policy now?
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Certifying configurable RTL & HWProcessACT, BrandingTSCmlEOYQ4-2020EOYAllen BaumDefine the process for configurable core IP to be licensed to use the trademarks.Part of Branding policy now?
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compatibility test planISAACTPriv, UnprivhlnowKen DockserDetermine the intent of compatibility tests, what scenarios will be tested, when sections will be rolled out (e.g., basic isolated instructions, basic interacting instructions, detailed corner cases)Should be the responsibility of the TGs creating instruction or feature
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Profile definitionISAPriv, UnprivhmnowKen DockserClearly define what a profile is, what it includes and what it doesn't, how/if it differs from a platform
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Test fixture for RTLISAACTPriv, Unprivhm
yesterday
Q4-2021 for limited versionKen DockserSample test harness for running compliance tests on RTL; includes interrupt generators, memory transactors, checkers, etc.Unclear if universal solution is possible.
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Question answering correctnessISAallFormalh?nowneeds rsrcongoingAllen BaumWhen a question is answered, formal model must be checked for agreement
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Priority
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lfuture
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m
in next 18 months
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h
in next 6 months
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Effort
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s< 1 month
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m< 6 months
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l
< 12 months
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xl> 12 months
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xxl> 2 years
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Skill Set AbbreviationsAarchitect
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BBootLoaders
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C
•Tool chain (e.g., gcc, optimizers, gdb, valgrind, …)
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D
Descriptions including Profiles, Test input, Config, etc.
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D
•Documentation (seasoned)
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HHypervisor
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I
•Real implementations as POC
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M
•Middleware and runtime libraries
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O
Operating Systems
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P
Application Performance
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S
•Emulator/simulator (spike, QEMU, etc.)
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T
•Compliance test writers
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VVirtual Machines
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