ABCDEFGHIJKLMNO
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offsetoffsetlenSATAPCIe
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bytebitwordbitbitsmoderst20100rst100typenamedescriptioncomment
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PLL config
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0000001rw00000boolENPLLEnable PLL
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0010011rw00000boolENPLLLDOEnable PLL LDO
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0020021rw00000boolENBGSC_REFEnable switched cap bias current module/REFGEN
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0030031rw00000boolAPLL_CP_CURRIncrease the APLL CP currentAdded after PG1.0. Presumably for a reason?
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0040041rw00000boolENDIGLDOEnable DIG LDO. Required to wake pll up for pll dig
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0050051rw11100u1C1_2XIncrease filter capacitance by 2x in low reference (20 MHz) clock:
0 = 120 pF for PCIe
1 = 240 pF for SATA and SSC		Sounds like this should be zero when using a 100 MHz refclk?
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0060062rw11100u2RESVALUESets loop filter resistor value:
0 = 1.00 kΩ for PCIe
1 = 1.67 kΩ for SATA
2 = 2.50 kΩ for SSC		Is this still right when using 100 MHz refclk for SATA?
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0100084rw00000u4CP_CTRLCharge pump control
0b0000 = Nom
0b0001 = +13%
0b0010 = +27%
0b0011 = +50%
0b0100 = −20%
0b1000 = −27%
0b1010 = −50%
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01400122rw33333u2EN_LATCHEnables output latch in differential ring to control power. Designer should be contacted while changing this value:
0 = All latch on
1 = Remove 33%
2 = Remove 16%
3 = Remove 50%
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01600141rw11111boolEN_MEASEnable measurement circuit inside APLL ANA to control AMUX output.Why is this enabled even though the AMUX output pads (U8, V8) are listed as "Reserved Pins - Leave unconnected" in the datasheet?
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01700151rw00000boolEN_RTRIMEnable resistor calibrationsince RTRIM control loop is configured for PCIe, shouldn't this be enabled then?
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02000161rw00000boolCLK_FLIPInvert clock output
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02100171rw00000boolPFD_CLRReset phase-frequency detector (open PLL loop)
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02200181rw00000boolEN_3PEnables the SC circuit in the APLL LFPG1.0 usage was for "3-phase ring oscillator". Still reflected in name.
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02300191rw00000boolDIS_REFCLKDisable CML that control FREF output clock buffer.
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02400202rw00000u2APLL_MISC_CTRL0 = No step
1 = 75% to 100%
2 = 75% to 87.5% to 100% in 60, 20 , 20 cycle steps
3 = same as 0b10 but in 40, 40, 40 cycle steps
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02600221rw00000u1APLL_MISC_CTRLpower saving :
0 = Default mode
1 = Used for debug
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02700231rw00000u1APLL_MISC_CTRL0 = fixed divider
1 = programmable divider
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03000241rw00000boolAPLL_MISC_CTRL50 MHz rtrim disable
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03100251rw00000u1APLL_MISC_CTRLlock speed :
0 = 128 clock
1 = 256 clock
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03200261rw00000u1TESTCLKMUXSELSelects test clock mux :
0 = REF Clock
1 = Divided clock
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03300271rw00000u1AMUXSELAMUX select :
0 = KVCO
1 = VRTRIM
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03400282rw00003TRM says reserved, but init procedure for PCIe sets these two bits with the comment "Configure proxy TXLDO and RXLDO enables"
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03600301rw10010boolDIGCLRZCLRZ for APLL DIG and DLL DIG. When low resets flops and state machines
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03700311rw11000u1SEL_IN_FREQSelect input frequency:
0 = 100 MHz
1 = 20 MHz		This probably selects which refclk input is used.
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0400401rw00000u1MDIVPULSEUpdate M div when pulse is high
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0410411rw00000boolENSSCEnable spread spectrum
31
0420421rw01100boolEN_CLK50mEnable 50 MHz clock (used by Ethernet)
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0430431rw01100boolEN_CLK100mEnable 100 MHz clock... for?
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0440441rw01100boolEN_CLK125mEnable 125 MHz clock (used by Ethernet)
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0450451rw01100boolEN_CLKAUXEnable auxiliary clock (testclk)?
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04604612rw00000u12MDIVFRACFractional part of feedback divider (osc/ref)
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06204188rw300300300100100u8MDIVINTInteger part of feedback divider (osc/ref). Must be >= 4.Ignored since fixed feedback divider is used
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07204264rw00000u4NP1_DIV_INTInteger part of N+1 divider
0 value maps to 1
4 value maps to 5
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07604301rw01000u1PLLREFSELChose reference clock value 0 = 100 MHz / 1 = 20 MHz (Note: only needs to be set if using fixed FB divider)
For fixed divider mode [31:30] defines division ratio as:
0b00 = 25
0b01 = 125
0b10 = 15
0b11 = 75
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07704311rw11100u1ENSATAMODEMode select:
0 = PCIe (2.5 GHz)
1 = SATA (1.5 GHz)
Used by APLLDIG and TRX_DIG for different purpose. Needs to configure this bit to get ethernet clocks
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Spread-spectrum config
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08008021rw00000u21SSCFRSPREADSSC frequency spread
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0a508213rw00000u3SSCEXPOExponent portion of the modified frequency in SSC operation
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0b008247rw00000u7SSCMANTMantissa portion of the modified frequency in SSC operation
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0b708311rw00000boolSSCDNSPREADSSC downspread
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PLL LDO config
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0c00c01rw00000u1PLLLDO_CTRL_0_UNUSED—
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0c10c15rw01616016u5PLLLDO_CTRL_TRIMTRIM_BITS vout:
 0 = 1.000V
 1 = 1.025V
...
16 = 1.400V
...
24 = 1.600V
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0c60c61rw01101boolPLLLDO_EN_LPEnable low power mode
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0c70c71rw01101boolPLLLDO_EN_BUF_CUREnable increased buffer current?
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0d00c81rw00000boolPLLLDO_EN_EXT_CAPEnable external cap mode
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0d10c91rw00000boolPLLLDO_EN_SC_PROTEnable short circuit protectionEnable? Disable more likely?
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0d20c101rw00000boolPLLLDO_EN_BYPASSEnable bypass mode (see warning below)
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0d30c111rw01101boolPLLLDO_EN_LDO_STABLELDO Stable Signal?
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0d40c121rw00000boolPLLLDO_EN_RETENTIONEnable retention mode
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0d50c133rw00000u3PLLLDO_CTRL_15_14_13—
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DIG LDO config
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0e00c165rw00000s5DIGLDO_VSETVDDAR adjustment:
−16 = 1.05V
−15 = 1.06V
 ...
 −1 = 1.20V
  0 = 1.21V (default)
 ...
 15 = 1.36V
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0e50c211rw00000boolDIGLDO_EN_LP_CAPLESSMODEEnables low power capless mode.
Quiescent LDO current decreases by 240μA typical.
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0e60c221rw01101boolDIGLDO_EN_CAPLESSMODEEnables capless mode. In particular:
1. The 800 fF capacitor between VDDAR and the gate of the power FET is bypassed.
2. The output of the error amplifier connects to a 30 pF capacitor which connects to VSSA via a 40 kΩ resistor. This resistor is also bypassed.		?
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0e70c231rw00000boolDIGLDO_EN_HP_CAPLESSMODEEnables high performance capless mode.
Quiescent LDO current increases by 240 μA.
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0f00c241rw00000boolDIGLDO_EN_SUB_REGULATIONDisables sub regulation
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0f10c251rw00000boolDIGLDO_DIS_SC_PROTDisables short circuit protection
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0f20c261rw10010boolDIGLDO_PULLDOWNZEnables LDO output pulldown
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0f30c271rw00000boolDIGLDO_BYPASSPuts the DIG LDO in bypass mode. Need to be careful while exercising this mode, the 1.8V external supply must be lowered before asserting this bit.
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0f40c284rw00000—
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VTUNE control loop
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1001004rw0000−4s4VTUNE_EXT_VALInitial control loop value: -4 (min) .. 0 (default) ... 4 (max)always seems to land at -4 if control loop enabled
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1041041rw00001boolVTUNE_MODEEnable loop in continuous mode (takes precedence over next bit)
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1051051rw00000boolVTUNE_MODEEnable loop until locked, then freeze
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1061061rw00000u1VTUNE_SPEED# of REFCLKs to wait after previous update:
0 = 128
1 = 256
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1071071rw00001u1VTUNE_EXT_ENSelect loop starting point.
0 = default 0000
1 = VTUNE_EXT_VAL
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1101082rw00000u2VTUNE_RANGE0 = 0.9-0.8
1 = 1.0-0.9
2 = 1.1-1.0
3 = 1.1-0.9
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RTRIM control loop
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11210104rw0000−8s4RTRIM_EXT_VALInitial control loop value: −8 (min) .. 0 (default) ... 7 (max)
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11610141rw00001boolRTRIM_MODEEnable loop in continuous mode (takes precedence over next bit)
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11710151rw00000boolRTRIM_MODEEnable loop until locked, then freeze
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12010161rw00000u1RTRIM_SPEED# of REFCLKs to wait after previous update:
0 = 128
1 = 256
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12110171rw00000u1RTRIM_EXT_ENSelect loop starting point.
0 = default 0000
1 = RTRIM_EXT_VAL
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12210182rw00000u2RTRIM_RANGE0 = 0.9-0.8
1 = 1.0-0.9
2 = 1.1-1.0
3 = 1.1-0.9
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AUX clock
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12410205rw00000u5AUX_DIVAux divider; Valid range is 2-31
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13110251rw00000u1AUX_CLK_SEL0=Divided, 1=ref-clk
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13210266rw00000—
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PLL status
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1401401r-00boolPLL_LOCKAPLL locked
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1411411r-00boolPLLSSC_ENSSC is engaged
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1421421r-00boolPLLANA_ENAnalog EN. Same as APLL DIG STS 4 internally
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1431431r-00boolPLLDIG_ENDigital EN. Same as APLL DIG STS 2 internally
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1441444r-00s4VTUNESTSValue of the vtune control loop (may not be static in continuous mode of operation)
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1501484r-00s4RTRIMSTSValue of the rtrim control loop (may not be static in continuous mode of operation)
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15414121r-00boolSATA: high when DIG on and reset, toggles when PLL enabled
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15514131r-00boolSATA: DIG on, very briefly low after turning PLL off
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15614141r-00boolSATA: briefly high after PLL enabled // PCIe: toggles when PLL enabled
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15714151r-00boolSATA: high when PLL enabled // PCIe: DIG on, very briefly low after turning PLL off
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160141616r-00—
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RX serdes status
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1801801r-00u1TESTFAILTest failure. Driven high when an error is encountered during a test sequence executed on channel i. Synchronous to RXBCLKIN[i].
98
18118131r-00—
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TX serdes status
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1c01c01r-00u1TESTFAILTest failure. Driven high when an error is encountered during a test sequence executed on channel i, or if an over or underflow occurs in the Tx serialiser when ENFTP = 0. Synchronous to TXBCLKIN[i].