muCPU isa

	A	B	C	D	E	F
1	Instruction					semantics
2	0	rs	rt	rd	0	sll rd = $s << $t
3	0	rs	rt	rd	1	srl rd = $s << $t
4	0	rs	rt	rd	2	add rd = $s + $t
5	0	rs	rt	rd	3	sub rd = $s - $t
6	0	rs	rt	rd	4	nand rd = !($s & $t)
7	0	rs	rt	rd	5	nor rd = !($s \| $t)
8	0	rs	rt	rd	6	and rd = $s & $t
9	0	rs	rt	rd	7	or rd = $s \| $t
10	1	rs	0	imm		bez $s==0? pc+= imm : pc++
11	1	rs	1	imm		bnez $s!=0? pc+= imm : pc++
12	1	rs	2	imm		bgez $s>=0? pc+= imm : pc++
13	1	rs	3	imm		blez $s<=0? pc+= imm : pc++
14	1	rs	4	imm		bgz $s>0? pc+= imm : pc++
15	1	rs	5	imm		blz $s<0? pc+= imm : pc++
16	1	rs	6	imm		ldi rs <= imm
17	2	rs	rt	imm		lb rt <= RAM[rs + imm]
18	3	rs	rt	imm		sb rt => RAM[rs + imm]
19	[15:14]	[13:11]	[10:8]	[7:5]	[4:0]
20	Revision 2.1 (dev version)
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