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DC-SCI Pin Definition 
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The DC-SCI connector pinout includes the single name (preferred board net name that include functional and directional nomenclature), gold finger lengths, single node usages, voltage, direction, typical usages and dual node usage.
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The contact sequence for each pin indicates the order in which the pins make contact between the HPM and the DC-SCM. The GND pins are required to be long pins or 1st mate. The PRSNT0_N/ PRSNT1_N pins and P12V_AUX pins are required to be short pins or 2nd mate. However, the remaining pins indicated as 2nd mate can be flexibly assigned as long pins/1st mate if dictated by design or DFM requirements.
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Multi-function DC-SCI pins list the functions in order starting with the most typical expected usage.
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When multiple voltages are listed for a signal, they map the respective alternate pin function order.
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DC-SCI Signal Descriptions 
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The following sections provide the signal descriptions of signals through the DC-SCI. 
The signal names are constructed using the notation of:
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 function_(bus source)_(signal source)_(signal destination)_Instance#_Partition#_Polarity  
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Note: Follow device datasheet recommendations to appropriately terminate un-used signals on the DC-SCM. 
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Abbreviation Definition: 
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Symbol Description
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_N or #  Denotes active low signal
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Input  Input to DC-SCM
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Output  Output from DC-SCM
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InOut At least one of the functions is a bidirectional signal
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CHANGES MADE
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8/24/2021Fixed SPI pin directions (bug)
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0.95cB47 Add UART1_HPM_SCM_RX
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" "B48 Add UART1_HPM_SCM_TX
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" "B51 - Add UART0_HPM_SCM_RX
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" "A63 - Add UART0_HPM_SCM_TX
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" "A60 Added alt function of SPI1_IRQ0_N to make SPI1 random access not polled.
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0.95dUpdated PECI voltage as a range copied from DC-SCMv1 spec vs simply 1.0
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" "Added MAIN Tab for overview
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OPENAspeed looking into if PCIE_SCM_HPM_CLK_100M input clock is needed through DC-SCI.
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FUTURE CONSIDERATIONS
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Dedicated ADC
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Dual partition support for dual TPM SPI busses
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VRef for busses like I3C
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