RD53_Configuration_Registers

	A	B	C	D	E	F	G	H	I	J	K	L	M	N	O
1	TMR	hex Address	dec Address	Register Name	Type	Size	Reset	Check	Unroll	Fields	Description	Default Value	Fields Description	Comment	Redundant

2	Pixel Matrix Section
3	TRUE	0	0	PIX_PORTAL	R/W	16		TRUE		[15:0]	Virtual register to access pixel matrix	16'b0
4	TRUE	1	1	REGION_COL	R/W	8		TRUE		[7:0]	Region Column Address	8'b0		CoreCol[5:0]=REGION_COL[7:2], RegionInCoreCol=REGION_COL[1], PixelPair=REGION_COL[0]
5	TRUE	2	2	REGION_ROW	R/W	9		TRUE		[8:0]	Region Row Address	9'b0		CoreRow[5:0]=REGION_ROW[8:3], RegionInCoreRow[2:0]=REGION_ROW[2:0]
6	TRUE	3	3	PIX_MODE	R/W	5		TRUE		{EnSEUCount,HitSampleMode,Broadcast,ConfWrConfig,AutoRow}	Pixel Operating modes	5'b0_1_0_1_0	Enable SEU counting, HitSampleMode = 1 only samples synchronous hits, Broadcast, ConfWrConfig = 1 writes Pixel Config (5-bits) ConfWrConfig = 0 writes FrontEnd Config (3-bits), Enable AutoRow	EnSEUCount to enable SEU error counting, HitSampleMode = 1 only samples synchronous hits, Broadcast, ConfWrConfig = 1 writes Pixel Config (5-bits) ConfWrConfig = 0 writes FrontEnd Config (3-bits), AutoRow
7	TRUE	4	4	PIX_DEFAULT_CONFIG	R/W	16		TRUE		[15:0]	Selects default configuration in Pixels	16'b0		To exit deault mode use 16'h9ce2 as a magic number
8	TRUE	5	5	PIX_DEFAULT_CONFIG_B	R/W	16		TRUE		[15:0]	Selects default configuration in Pixels	16'b0		To exit deault mode use 16'h631d as a magic number
9	TRUE	6	6	GCR_DEFAULT_CONFIG	Magic Number	16		TRUE		[15:0]	Selects default configuration	16'b0		To exit deault mode use 16'hac75 as a magic number (without Reset)
10	TRUE	7	7	GCR_DEFAULT_CONFIG_B	Magic Number	16		TRUE		[15:0]	Selects default configuration	16'b0		To exit deault mode use 16'h538a as a magic number (without Reset)
11	Front End Section
12	TRUE	8	8	DAC_PREAMP_L_DIFF	R/W	10		TRUE		[9:0]	Preamp input stage current left edge pixels (2 pixel columns)	10'd50
13	TRUE	9	9	DAC_PREAMP_R_DIFF	R/W	10		TRUE		[9:0]	Preamp input stage current right edge pixels (2 pixel columns)	10'd50
14	TRUE	A	10	DAC_PREAMP_TL_DIFF	R/W	10		TRUE		[9:0]	Preamp input stage current top-left corner pixels (2x2 pixels)	10'd50
15	TRUE	B	11	DAC_PREAMP_TR_DIFF	R/W	10		TRUE		[9:0]	Preamp input stage current top-right corner pixels (2x2 pixels)	10'd50
16	TRUE	C	12	DAC_PREAMP_T_DIFF	R/W	10		TRUE		[9:0]	Preamp input stage current top row pixels (2 pixel rows)	10'd50
17	TRUE	D	13	DAC_PREAMP_M_DIFF	R/W	10		TRUE		[9:0]	Preamp input stage current for all pixels except edge/top/corners	10'd50
18	TRUE	E	14	DAC_PRECOMP_DIFF	R/W	10		TRUE		[9:0]	Precomparator tail current	10'd50
19	TRUE	F	15	DAC_COMP_DIFF	R/W	10		TRUE		[9:0]	Comparator total current	10'd50
20	TRUE	10	16	DAC_VFF_DIFF	R/W	10		TRUE		[9:0]	Preamp feedback current (return to baseline)	10'd100
21	TRUE	11	17	DAC_TH1_L_DIFF	R/W	10		TRUE		[9:0]	Negative branch voltage offset for left edge pixels (2 pixel columns)	10'd100
22	TRUE	12	18	DAC_TH1_R_DIFF	R/W	10		TRUE		[9:0]	Negative branch voltage offset for right edge pixels (2 pixel columns)	10'd100
23	TRUE	13	19	DAC_TH1_M_DIFF	R/W	10		TRUE		[9:0]	Negative branch voltage offset for all pixels except edge	10'd100
24	TRUE	14	20	DAC_TH2_DIFF	R/W	10		TRUE		[9:0]	Positive branch voltage offset	10'd0
25	TRUE	15	21	DAC_LCC_DIFF	R/W	10		TRUE		[9:0]	Leakage current compensation current	10'd100
26	TRUE	16	22	DAC_PREAMP_L_LIN	R/W	10		TRUE		[9:0]	Preamp input stage current left edge pixels (2 pixel columns)	10'd150
27	TRUE	17	23	DAC_PREAMP_R_LIN	R/W	10		TRUE		[9:0]	Preamp input stage current right edge pixels (2 pixel columns)	10'd150
28	TRUE	18	24	DAC_PREAMP_TL_LIN	R/W	10		TRUE		[9:0]	Preamp input stage current top-left corner pixels (2x2 pixels)	10'd150
29	TRUE	19	25	DAC_PREAMP_TR_LIN	R/W	10		TRUE		[9:0]	Preamp input stage current top-right corner pixels (2x2 pixels)	10'd150
30	TRUE	1A	26	DAC_PREAMP_T_LIN	R/W	10		TRUE		[9:0]	Preamp input stage current top row pixels (2 pixel rows)	10'd150
31	TRUE	1B	27	DAC_PREAMP_M_LIN	R/W	10		TRUE		[9:0]	Preamp input stage current for all pixels except edge/top/corners	10'd150
32	TRUE	1C	28	DAC_FC_LIN	R/W	10		TRUE		[9:0]	Folded cascode branch current	10'd20
33	TRUE	1D	29	DAC_KRUM_CURR_LIN	R/W	10		TRUE		[9:0]	Krummenaker feedback current (return to baseline)	10'd70
34	TRUE	1E	30	DAC_REF_KRUM_LIN	R/W	10		TRUE		[9:0]	Krummenacher reference voltage	10'd360
35	TRUE	1F	31	DAC_COMP_LIN	R/W	10		TRUE		[9:0]	Comparator current	10'd80
36	TRUE	20	32	DAC_COMP_TA_LIN	R/W	10		TRUE		[9:0]	Comparator output stage current	10'd900
37	TRUE	21	33	DAC_GDAC_L_LIN	R/W	10		TRUE		[9:0]	Global threshold for left edge pixels (2 pixel columns)	10'd900
38	TRUE	22	34	DAC_GDAC_R_LIN	R/W	10		TRUE		[9:0]	Global threshold for right edge pixels (2 pixel columns)	10'd900
39	TRUE	23	35	DAC_GDAC_M_LIN	R/W	10		TRUE		[9:0]	Global threshold for all pixels except edge	10'd900
40	TRUE	24	36	DAC_LDAC_LIN	R/W	10		TRUE		[9:0]	Local threshold current	10'd130
41	TRUE	25	37	LEACKAGE_FEEDBACK	R/W	2		TRUE		{CFG_VCTRL_LCC,CFG_VCTRL_CF0}	Leakage current compensation and feedback capacitance connection	2'd0	Connect leakage current comp. circuit, Connect feedback capacitance
42	Power Section
43	TRUE	26	38	VOLTAGE_TRIM	R/W	10		TRUE		{EN_ILIM_VREFA,EN_ILIM_VREFD,TRIM_VREFA[3:0],TRIM_VREFD[3:0]}	Voltage trim register	10'b00_1000_1000	Enable Analog current limit, Enable Digital current limit, Analog voltage regulator trim, Digital voltage regulator trim
44	Digital Matrix Section
45	TRUE	27	39	EnCoreCol_3	R/W	6		TRUE	TRUE	{EnCoreCol[53:48]}	Enable Core Column: from 48 to 53	6'b01_0010		One column out of three is enabled
46	TRUE	28	40	EnCoreCol_2	R/W	16		TRUE	TRUE	{EnCoreCol[47:32]}	Enable Core Column: from 32 to 47	16'b0100_1001_0010_0100		One column out of three is enabled
47	TRUE	29	41	EnCoreCol_1	R/W	16		TRUE	TRUE	{EnCoreCol[31:16]}	Enable Core Column: from 16 to 31	16'b1001_0010_0100_1001		One column out of three is enabled
48	TRUE	2A	42	EnCoreCol_0	R/W	16		TRUE	TRUE	{EnCoreCol[15:0]}	Enable Core Column: from 0 to 15	16'b0010_0100_1001_0010		One column out of three is enabled
49	TRUE	2B	43	EnCoreColumnReset_3	R/W	6		TRUE	TRUE	{EnCoreColumnReset[53:48]}	Enable Core Column Reset: from 48 to 53	6'b0
50	TRUE	2C	44	EnCoreColumnReset_2	R/W	16		TRUE	TRUE	{EnCoreColumnReset[47:32]}	Enable Core Column Reset: from 32 to 47	16'b0
51	TRUE	2D	45	EnCoreColumnReset_1	R/W	16		TRUE	TRUE	{EnCoreColumnReset[31:16]}	Enable Core Column Reset: from 16 to 31	16'b0
52	TRUE	2E	46	EnCoreColumnReset_0	R/W	16		TRUE	TRUE	{EnCoreColumnReset[15:0]}	Enable Core Column Reset: from 0 to 15	16'b0
53	Functions Section
54	TRUE	2F	47	TriggerConfig	R/W	10		TRUE		{TwoLevelTrigger,LatencyConfig[8:0]}	Trigger Configuration	10'b0_111110100	Trigger Mode selection, Latency Configuration
55	TRUE	30	48	SelfTriggerConfig_1	R/W	6		TRUE		{SelfTriggerEn,HitOrDigThrEn,HitOrDigThr[3:0]}	Self Triggering Configuration (2 of 2)	6'b0_1_0001	Enable Self Triggering,Enable threshold on HitOr, HitOr digital threshold	By default Self Triggering is Off
56	TRUE	31	49	SelfTriggerConfig_0	R/W	15		TRUE		{SelfTriggerDelay[9:0],SelfTriggerMultiplier[4:0]}	Self Triggering Configuration (1 of 2)	15'b0001100100_00001	Self Triggering delay, Self Triggering multiplier	10'd100,5'd1
57	TRUE	32	50	SelfTriggerDeadTime	R/W	16		TRUE		[15:0]	Throttle SelfTrigger rate	16'b0	Allows to throttle SelfTrigger rate	Zero means no throttling
58	TRUE	33	51	HitOrPatternLUT	R/W	16		TRUE		[15:0]	HitOr pattern look up table	16'b0		All zero by default
59	TRUE	34	52	ReadTriggerConfig	R/W	14		TRUE		{DataReadDelay[1:0],ReadTriggerTimeout[11:0]}	Delay between reads in column, Read Trigger Configuration	14'b00_001111101000	Data Read Delay, Read Trigger Timeout	ReadTriggerTimeout = 1000
60	TRUE	35	53	TruncationTimeoutConf	R/W	12		TRUE		[11:0]	Timeout for Event Truncation	12'b0
61	TRUE	36	54	CalibrationConfig	R/W	8		TRUE		{DigitalInjectionEnable, AnalogInjectionMode, CalEdgeFineDelay[5:0]}	Calibration Configuration	8'b0_1_000000	Enable Digital injection, Analog injection Mode, CalEdge fine delay	By default inject analog with zero delay
62	TRUE	37	55	CLK_DATA_FINE_DELAY	R/W	12		TRUE		{ClkFineDelay[5:0], DataFineDelay[5:0]}	Clock and Data fine delay	12'b0	Clock fine delay, Data fine delay	Zero delay by default
63	TRUE	38	56	VCAL_HIGH	R/W	12		TRUE		[11:0]	VCAL high	12'd500
64	TRUE	39	57	VCAL_MED	R/W	12		TRUE		[11:0]	VCAL med	12'd300
65	TRUE	3A	58	MEAS_CAP	R/W	3		TRUE		{EN_INJCAP_PAR_MEAS, EN_INJCAP_MEAS, SEL_CAL_RANGE}	Measure Injection Parasitic Capacitor and CALIB DACs range	3'b0	Enable Measure Injection Parasitic Capacitor, Enable Measure Injection Capacitor, Select CALIB DACs range (0=VREF/2 1=VREF)
66	TRUE	3B	59	CdrConf	R/W	4		TRUE		{CdrSelPd,CdrSelSerClk[2:0]}	CDR Configuration	4'b0_000	CdrSelPd, Select Cdr Ser Clock	OverwriteCdrLimit is not present in this chip
67	TRUE	3C	60	ClockEnableConf	R/W	12		TRUE		{EnClk40[2:0],EnClk160[2:0],EnClkDataMerging[2:0],EnClkAurora[2:0]}	Enable single clocks for all four clock domains.	12'b111_111_111_111	Enable 40MHz clk, Enable 160 MHz clk, Enable data merging clk, Enable Aurora clk	This option is not used in the current chip
68	TRUE	3D	61	ChSyncConf	R/W	5		TRUE		{ChSyncThreshold[4:0]}	Threshold settings for the Channel Synchronizer	5'b10000		Low threshold (16), while High threshold is ChSyncThreshold * 2 (32)
69	TRUE	3E	62	GlobalPulseConf	R/W	16		TRUE		[15:0]	Global pulse routing select	16'b0
70	TRUE	3F	63	GlobalPulseWidth	R/W	9		TRUE		[8:0]	Length of the Global Pulse	9'b0_0000_0001	110010	GlobalPulseWidth, computed with 40 MHz clock. If the value is zero it will be treated as 1 (zero has no meaning).
71	TRUE	40	64	ServiceDataConf	R/W	9		TRUE		{EnServiceData,ServiceFrameSkip[7:0]}	ServiceData Configuration	9'b1_00110010	Enable ServiceData block, How many Data frames to skip before sending a Monitor Frame	EnServiceData is Off. Send a ServiceData frame every 50 Data Frames
72	TRUE	41	65	ToTConfig	R/W	13		TRUE		{EnPToTClk640,ToAEnable,ToTDualEdgeCount,ToT6to4Mapping,PToTLatencyAdjust[8:0]}	ToT Configuration	13'd0	Enable PToT clk (640 MHz), Enable ToA, Enable ToT DualEdge count, Enable 6to4 ToT mapping, Set PToT Latency
73	TRUE	42	66	PrecisionToTEnable_3	R/W	6		TRUE	TRUE	{PToTEnable[53:48]}	Enable Precision ToT: from 48 to 53	6'b0
74	TRUE	43	67	PrecisionToTEnable_2	R/W	16		TRUE	TRUE	{PToTEnable[47:32]}	Enable Precision ToT: from 32 to 47	16'b0
75	TRUE	44	68	PrecisionToTEnable_1	R/W	16		TRUE	TRUE	{PToTEnable[31:16]}	Enable Precision ToT: from 16 to 31	16'b0
76	TRUE	45	69	PrecisionToTEnable_0	R/W	16		TRUE	TRUE	{PToTEnable[15:0]}	Enable Precision ToT: from 0 to 15	16'b0
77	TRUE	46	70	DataMerging	R/W	13		TRUE		{DataMergingInputPolarityInvert[3:0],EnOutputDataChipId,EnGatingDataMergeClk1280,SelDataMergeClk,EnDataMergeLane[3:0],MergeChBonding,DataMergingGpoSel}	Data Merging Configuration	13'b0000_1_1_0_0000_0_1	Invert the polarity of input signals to DataMerger, Enable ChipID in output data, Enables Gating of 1280 MHz Data Merge clock, Select Data Merge Clock (0:640 1:1280), Which of the Data Mergers are enabled, Selects if first two inputs are bonded, Which word to route to GPO	SelDataMergeClk = 0 640MHz, SelDataMergeClk =1 1280 MHz. EnGatingDataMergeClk1280 = 0 Enables deserializer, EnGatingDataMergeClk1280 = 1 disables it.
78	TRUE	47	71	IOLaneMappingMux	R/W	16		TRUE		{InLaneMux_3[1:0],InLaneMux_2[1:0],InLaneMux_1[1:0],InLaneMux_0[1:0],OutLaneMux_3[1:0],OutLaneMux_2[1:0],OutLaneMux_1[1:0],OutLaneMux_0[1:0]}	Mux selection for Input and Output Lane mapping	16'b11_10_01_00_11_10_01_00	InLaneMux_3, InLaneMux_2, InLaneMux_1, InLaneMux_0, OutLaneMux_3, OutLaneMux_2, OutLaneMux_1, OutLaneMux_0	InN -> LaneN, OutN -> LaneN
79	TRUE	48	72	EnCoreColumnCalibration_3	R/W	6		TRUE	TRUE	{EnCoreColumnCalibration[53:48]}	Enable calibration at CoreColumn level: from 48 to 53	6'h3f		All enabled by default
80	TRUE	49	73	EnCoreColumnCalibration_2	R/W	16		TRUE	TRUE	{EnCoreColumnCalibration[47:32]}	Enable calibration at CoreColumn level: from 32 to 47	16'hffff		All enabled by default
81	TRUE	4A	74	EnCoreColumnCalibration_1	R/W	16		TRUE	TRUE	{EnCoreColumnCalibration[31:16]}	Enable calibration at CoreColumn level: from 16 to 31	16'hffff		All enabled by default
82	TRUE	4B	75	EnCoreColumnCalibration_0	R/W	16		TRUE	TRUE	{EnCoreColumnCalibration[15:0]}	Enable calibration at CoreColumn level: from. 0 to 15	16'hffff		All enabled by default
83	TRUE	4C	76	DataConcentratorConf	R/W	11		TRUE		{EnCRC,EnBCId,EnLv1Id,NumOfEventsInStream[7:0]}	DataConcentrator Configuration	11'b0_0_0_00000000	Enable CRC, Enable BCId, Enable Lv1Id, maximim number of events in a Stream	EnCRC, EnBCID, EnLv1Id are NOT connected (but implemented) in the ATLAS implementation of RD53B
84	TRUE	4D	77	CoreColEncoderConf	R/W	16		TRUE		{BinaryReadOut,RawData,MaxHits[8:0],MaxToT[2:0],ToTRemoval,SensorGeometry}	CoreColumnEncoder configuration options	16'b0_0_000000000_000_0_1	Enable binary readout, Output raw data, Maximum number of Hits, Maximum ToT value,Remove hits only looking at ToT value,Sensor geometry 1=square 0=rectangular	All features are disabled by default
85	TRUE	4E	78	EnHitsRemoval_3	R/W	6		TRUE	TRUE	{EnHitsRemoval[53:48]}	Enable Hits removal at CoreColumn level: from 48 to 53	6'b0
86	TRUE	4F	79	EnHitsRemoval_2	R/W	16		TRUE	TRUE	{EnHitsRemoval[47:32]}	Enable Hits removal at CoreColumn level: from 32 to 47	16'b0
87	TRUE	50	80	EnHitsRemoval_1	R/W	16		TRUE	TRUE	{EnHitsRemoval[31:16]}	Enable Hits removal at CoreColumn level: from 16 to 31	16'b0
88	TRUE	51	81	EnHitsRemoval_0	R/W	16		TRUE	TRUE	{EnHitsRemoval[15:0]}	Enable Hits removal at CoreColumn level: from 0 to 15	16'b0
89	TRUE	52	82	EnIsolatedHitRemoval_3	R/W	6		TRUE	TRUE	{EnIsolatedHitRemoval[53:48]}	Enable Isolated Hits removal at CoreColumn level: from 48 to 53	6'b0
90	TRUE	53	83	EnIsolatedHitRemoval_2	R/W	16		TRUE	TRUE	{EnIsolatedHitRemoval[47:32]}	Enable Isolated Hits removal at CoreColumn level: from 32 to 47	16'b0
91	TRUE	54	84	EnIsolatedHitRemoval_1	R/W	16		TRUE	TRUE	{EnIsolatedHitRemoval[31:16]}	Enable Isolated Hits removal at CoreColumn level: from 16 to 31	16'b0
92	TRUE	55	85	EnIsolatedHitRemoval_0	R/W	16		TRUE	TRUE	{EnIsolatedHitRemoval[15:0]}	Enable Isolated Hits removal at CoreColumn level: from 0 to 15	16'b0
93	TRUE	56	86	EvenMask	R/W	16		TRUE		[15:0]	Even Pixel Mask for Isolated Hit Removal	16'b0		No neighbours at startup
94	TRUE	57	87	OddMask	R/W	16		TRUE		[15:0]	Odd Pixel Mask for Isolated Hit Removal	16'b0		No neighbours at startup
95	TRUE	58	88	EfusesConfig	R/W	16		TRUE		[15:0]	Efuses Op Mode [Read=0F0F, Write=F0F0]	16'b0		Deafult ot IDLE, ReadMode 16'h0f0f, WriteMode 16'hf0f0
96	TRUE	59	89	EfusesWriteData1	R/W	16		TRUE	TRUE	{EfusesWriteData[31:16]}	Data to be written to the Efuses	16'b0
97	TRUE	5A	90	EfusesWriteData0	R/W	16		TRUE	TRUE	{EfusesWriteData[15:0]}	Data to be written to the Efuses	16'b0
98	TRUE	5B	91	PhaseDetectorConfig	R/W	13		TRUE		{FixedMode,ManualMode[3:0],ManualChoice[7:0]}	Allows to configure the PhaseDetector behaviour of the DataMerging deserializer	13'b0	FixedMode disables automatic Phase jumps, Manual mode allows to select phase using ManualChoice, ManualChoice is the applied choice
99	TRUE	5C	92	AuroraConfig	R/W	14		TRUE		{SendAltOutput,EnablePRBS,ActiveLanes[3:0],CCWait[5:0], CCSend[1:0]}	Aurora configuration bits	14'b0_0_1111_011001_11	Send alternate output, Enable PRBS, Number of active lanes, CCWait, CCSend
100	TRUE	5D	93	AURORA_CB_CONFIG1	R/W	8		TRUE	TRUE	{CBWait[19:12]}	Aurora Channel Bonding configuration bits	8'hff