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GroupMilestoneDue DateDoneOwnersNotes
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2TestingSpec Exchange Format for CGRA2/14/18Taeyoung, Lenny, Pathttps://github.com/StanfordAHA/CGRAFlow/issues/56
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3TestingCreate testing environment2/21/18xLenny, Pathttps://github.com/StanfordAHA/CGRAFlow/issues/45
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4TestingRandom Graphs for PnR Testing3/21/18Lenny, Calebhttps://github.com/StanfordAHA/CGRAFlow/issues/51
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5TestingTests (directed tests)2/28/18SR, Lennyhttps://github.com/StanfordAHA/CGRAFlow/issues/47
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6TestingHalide -> coreir - test all halide functionality (Simulation)2/9/18xJeff, Ross, Dillonhttps://github.com/StanfordAHA/CGRAFlow/issues/48
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7Testing/FormalCoreIR -> simulate/smt post mapped graph3/21/18Ross, Dillonhttps://github.com/StanfordAHA/CGRAFlow/issues/49
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8FormalCompare input to output of coreir passes using SMT2/14/18Cristian, Ross, Lennyhttps://github.com/StanfordAHA/CGRAFlow/issues/50
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9FormalHalide -> coreir - test all halide functionality (SMT)2/28/18Jeff, Ross, Cristian
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10FormalConvert fabric into SMT2/21/18Cristian, Ross, Lennyhttps://github.com/StanfordAHA/CGRAFlow/issues/46
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12CGRAnbdev2: I/O pads, global stall network1/24/18xNikhilRELEASED and currently passing core tests as master (2/8)
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13CGRAnbdev3: mem almost-full/empty, OR signals instead of mux1/31/18Nikhil
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14CGRAnbdev4: updated/final PE spec, global control2/7/18Nikhil, Taeyoung
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15CGRAnbdev5: JTAG2/14/18Nikhil, Alex
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13CGRAnbdev3: updated/final PE spec, global control, JTAG2/7/18xNikhil, Alex, Taeyoung
RELEASED/debugging: https://travis-ci.org/StanfordAHA/CGRAGenerator/builds/338751621
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13CGRAnbdev4: mem almost-full/empty, OR signals instead of mux2/14/18Nikhil
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16CGRAnbdev5: multirate support2/21/18Nikhil, Ankita
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17CGRA2/28 DESIGN FREEZE2/28/18Nikhil
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19HalideFix Halide compilation bug (relocation in section...)2/5/18xJeff
MERGED: Breaks flow for all tests => needed to compile using a "trusty" machine since upgraded kiwi is using "xenial"
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20HalideAdd bool test to flow2/7/18~Jeff
DEBUGGING: Tests flow for onebit operators and comparisons => BitIO support needed in PnR
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21HalideAdd stereo test to flow2/14/18xJeffMERGED: large test that will challenge PnR => sent to PnR
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22HalideAdd unit tests for all Halide functionality2/14/18~Jeff
TESTING: test all functions in Halide using bundled tests (arith, bool, comp, unsigned/signed...) => Found and fixed simple multiple Codegen bugs; handed off to Mapping
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23HalideConnect linebuffer valids together; add cascade test2/21/18~Jeff
Properly connects linebuffer valids together and to output (results in test env change) => compiler has CoreIRValid feature, connects valid to wen; need rowbuffer change in CoreIR
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24HalideCreate scalable linebuffer test: chain of convolutions2/21/18xJeff
MERGED: Creates a scalable function to test scalability of PnR and CGRA grid sizing parameters => Created using array of Halide Funcs and #defines
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25HalideAdd harris application2/28/18xJeffCombines onebit, cascaded linebuffers, and a larger application size for PnR
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26HalideAdd multi-rate convolution (3x3 conv with 3 multipliers)2/28/18>>Jeff, Ross
Creates mapping challenge for accumulation and muxed registers => moved to next tapeout
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27HalideConvert all Halide interpreter tests to use fast sim3/7/18Jeff, DillonMakes testing larger images and coreir graphs feasible
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28HalideRandom Halide graph generator for testing3/21/18Jeff, LennyIn similar vein to PnR tests, make sure random Halide apps can be mapped
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30CoreIR/MapperGet stereo mapped2/9/18Ross
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31CoreIR/MapperUpdate mapper for PE from nbdev32/15/18Ross
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32CoreIR/MapperGet harris mapped2/22/18Ross
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33CoreIR/MapperGet Multi-rate convolution mapped3/3/18Ross
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34CoreIR/MapperAdd Stall capabilities to Mapper3/15/18Ross
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PNRParse new cgra_info.txt without io tiles yet 2/5/18XMakaiGet master passing with the new cgra_info.txt, still using IO hack
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36PNRAdd support for IO tiles2/13/18Makai, CalebMinimal changes needed to support new IO tiles and remove old hacks
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37PNRPrototype new placement decision procedure3/1/18CalebImproving placement speed with custom decision procedure
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38PNRFirst pass at timing constraints3/23/18Makai, CalebWe're blocked on this task until we have timing information
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