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BeagleBone Expansion Header PRU GPIO
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BeagleBone Expansion Header PRU GPIO Pins
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Note:
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PRU GPIO are read (input) from signals mapped to R31 register and set (output) by signals mapped to the R30 register. The "Type" column below indicates which signal can be connected to the pin.

Yellow highlighted pins require muxing in the PRU. See Chapter 4 in the AM335x PRU Reference Guide [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf].

Notice that the Pin mux mode must be changed to go between input and output. Unfortunately, the pin configuration register is located in priviledged memory, and in inaccessible by the PRU. This means that for true I/O, such as with MDIO, a kernel driver, or something outside the PRU, must handle swapping a pin between input and output. A simple interrupt handler, either in kernel space or user space (using the PRUSS_UIO driver found in the TI AM335X package), can take care of this by responding to interrupts from the PRU.
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PRU0PRU1
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Expansion header P8
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Header Pin #
Header Pin Name
PRUPRU GPIOTypeChip Pin Name
Pin Mux Mode
10
11gpio1_13015OGPMC_AD136
11
12gpio1_12014OGPMC_AD126
12
15gpio1_15015IGPMC_AD156
13
16gpio1_14014IGPMC_AD146
14
20gpio1_31113OGPMC_CSn25
15
I6
16
21gpio1_30112OGPMC_CSn15
17
I6
18
27gpio2_2218OLCD_VSYNC5
19
I6
20
28gpio2_24110OLCD_PCLK5
21
I6
22
29gpio2_2319OLCD_HSYNC5
23
I6
24
30gpio2_25111OLCD_AC_BIAS_EN5
25
I6
26
39gpio2_1216OLCD_DATA65
27
I6
28
40gpio2_1317OLCD_DATA75
29
I6
30
41gpio2_1014OLCD_DATA45
31
I6
32
42gpio2_1115OLCD_DATA55
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I6
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43gpio2_812OLCD_DATA25
35
I6
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44gpio2_913OLCD_DATA35
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I6
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45gpio2_610OLCD_DATA05
39
I6
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46gpio2_711OLCD_DATA15
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I5
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Expansion header P9
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Header Pin #
Header Pin Name
PRUPRU GPIOTypeChip Pin Name
Pin Mux Mode
45
24uart1_txd016IUART1_TXD6
46
25gpio3_2107OMCASP0_AHCLKX5
47
I6
48
26uart1_rxd116IUART1_RXD6
49
27gpio3_1905OMACSP0_FSR5
50
I6
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28SPI1_CS003OMCASP0_AHCLKR5
52
I6
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29SPI1_D001OMCASP0_FSX5
54
I6
55
30SPI0_D102OMCASP0_AXR05
56
I6
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31SPI1_SCLK00OMCASP0_ACLKX5
58
I6
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PRU Pins