BeagleBone Expansion Header PRU GPIO

	A	B	C	D	E	F	G
1	BeagleBone Expansion Header PRU GPIO Pins
2
3	Note:
4	PRU GPIO are read (input) from signals mapped to R31 register and set (output) by signals mapped to the R30 register. The "Type" column below indicates which signal can be connected to the pin. Yellow highlighted pins require muxing in the PRU. See Chapter 4 in the AM335x PRU Reference Guide [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf]. Notice that the Pin mux mode must be changed to go between input and output. Unfortunately, the pin configuration register is located in priviledged memory, and in inaccessible by the PRU. This means that for true I/O, such as with MDIO, a kernel driver, or something outside the PRU, must handle swapping a pin between input and output. A simple interrupt handler, either in kernel space or user space (using the PRUSS_UIO driver found in the TI AM335X package), can take care of this by responding to interrupts from the PRU.
5
6	PRU0	PRU1
7
8	Expansion header P8
9	Header Pin #	Header Pin Name	PRU	PRU GPIO	Type	Chip Pin Name	Pin Mux Mode
10	11	gpio1_13	0	15	O	GPMC_AD13	6
11	12	gpio1_12	0	14	O	GPMC_AD12	6
12	15	gpio1_15	0	15	I	GPMC_AD15	6
13	16	gpio1_14	0	14	I	GPMC_AD14	6
14	20	gpio1_31	1	13	O	GPMC_CSn2	5
15					I		6
16	21	gpio1_30	1	12	O	GPMC_CSn1	5
17					I		6
18	27	gpio2_22	1	8	O	LCD_VSYNC	5
19					I		6
20	28	gpio2_24	1	10	O	LCD_PCLK	5
21					I		6
22	29	gpio2_23	1	9	O	LCD_HSYNC	5
23					I		6
24	30	gpio2_25	1	11	O	LCD_AC_BIAS_EN	5
25					I		6
26	39	gpio2_12	1	6	O	LCD_DATA6	5
27					I		6
28	40	gpio2_13	1	7	O	LCD_DATA7	5
29					I		6
30	41	gpio2_10	1	4	O	LCD_DATA4	5
31					I		6
32	42	gpio2_11	1	5	O	LCD_DATA5	5
33					I		6
34	43	gpio2_8	1	2	O	LCD_DATA2	5
35					I		6
36	44	gpio2_9	1	3	O	LCD_DATA3	5
37					I		6
38	45	gpio2_6	1	0	O	LCD_DATA0	5
39					I		6
40	46	gpio2_7	1	1	O	LCD_DATA1	5
41					I		5
42
43	Expansion header P9
44	Header Pin #	Header Pin Name	PRU	PRU GPIO	Type	Chip Pin Name	Pin Mux Mode
45	24	uart1_txd	0	16	I	UART1_TXD	6
46	25	gpio3_21	0	7	O	MCASP0_AHCLKX	5
47					I		6
48	26	uart1_rxd	1	16	I	UART1_RXD	6
49	27	gpio3_19	0	5	O	MACSP0_FSR	5
50					I		6
51	28	SPI1_CS0	0	3	O	MCASP0_AHCLKR	5
52					I		6
53	29	SPI1_D0	0	1	O	MCASP0_FSX	5
54					I		6
55	30	SPI0_D1	0	2	O	MCASP0_AXR0	5
56					I		6
57	31	SPI1_SCLK	0	0	O	MCASP0_ACLKX	5
58					I		6