DDR5 Timing Calculator for AMD V0009.xlsx

	A	B	C	D	E	F	G	H	I	J
1	DDR5 Timing Calculator for AMD by RedF & Wolf87, Guided by Veii
2	Please make a local copy and edit it locally. Online, several users at the same time will only cause confusion.								Version 0.0.09
3	Primary Timings	use this formula at your own risk	equals in ns	MT/s	6600	calculated	Edit	do not touch !
4	tCL	28	8.48	UCLK 1:1	3300
5	tRCDWR	38	11.52	FCLK for best latency (3:2)	2200
6	tRCDRD	38	11.52	very small impact
7	tRP	38	11.52
8	tRTP	16
9	tWR	48	tWR Rule is not under 48, but 24 is somewhat an option
10	toogle switch for tWR (switch between 48 or fail safe variante ) 1=48 0=failsafe	1
11
12	minimum tRAS	54	tRCD	tRTP
13	tRCD+tRTP	54	38	16
14
15	optimum tRAS	64	tRCD	tRTP	BurstLength 16 / 2 = BurstChop	X = + 2 or 4 Points, minimum = 0
16	tRCD + tRTP + BurstChop + X	64	38	16	8	2
17
18	safe tRAS		tCWL	tRCDWR	tWR	this variant garants always a ROW Hit
19	tCWL+tRCDWR+tWR	112	26	38	48
20	tRC = tRAS, for safe tRAS	112	26	38	48
21
22	tRC = for tRAS minimum or optimum	tRC = for tRAS min	tRC = for tRAS Optimum
23	tRC = for tRAS minimum or optimum	92	102
24
25	tFAW	32	for all of our DIMMs ~ 32. 32 for 1kb pagesize dimms 48 for 2kb pagesize dimms. // As long as it is not confirmed that AMD uses 2 MC links each DIMM, the value is 32/48 instead of 16/24 :)
26
27	tRFC	choose your clock value and your tRFC for your Dimm type. tRFC depends on tREFI	Hynix A-Die [ns]	Hynix M-Die [ns]	Samsung B-Die [ns]	Samsung D-Die [ns]	Micron A+G REV [ns]	Micron Rev B [ns]	if you stay with 65535 maxed, is 320,352,384,416 If you want to give 65528 a try , then its 308, 340, 372 ,404 ~ pick one that suits you Scale both sets +/- 32. But keep values. Just test what REFI brings you most consistency(not latency)
28	DDR5 MT/s (MHz)	6600	160	220					IC Vendor Rating & JEDEC QC Pass @ 1.1v
29		0.30303030303 ns/tCK	120	160	260	270	260	360	Community researched minimums
30	tRFC [tREFi 65535]	429	130.0	130.0	130.0	130.0	130.0	130.0	if you use tREFi 65535, red value=if you reach min Value
31	tRFC [tREFi 65528]	404	122.4	122.4	122.4	122.4	122.4	122.4	if you use tREFi 65528, red value=if you reach min Value
32
33	RFCpb/sb		ns -> nCK Timing Value [Bios Entry]
34	WIP	JEDEC inspired	429.00 nCK	627.00 nCK	759.00 nCK	792.00 nCK	759.00 nCK	1089.00 nCK	<- needs formula help // 2GB IC , steps 16 (round up) / 3GB ICs , steps 24 (round up)
35	WIP	Community	330.00 nCK	330.00 nCK	330.00 nCK	330.00 nCK	330.00 nCK	330.00 nCK
36										[V]
37	tRRD_S/DG	8
38	tRRD_L/SG	12	recommended 12
39	tWTR_S/DG	7	Veii tweak: (can also be run at 4) "Thanks to this I have found a "small" exploit of my own. DDR4 & DDR5 can execute within 2 writes per read. Actually a little more, but they can do 2. As an example: RRDS 8 RRDL 12 WTRS 4 WTRL 24 RDRDSCL = (CCDL) 12-(RdBurstChop) 8+(OdtEnDly) 1 = 5 That is, If CCDLWR is used and WTRL would be exactly double of RRDL (normal) If the SC_Longs are also correct (the minimums) and RTP is not too low. Then the loop ends at exactly the right time to run WTRS at half clock. If not, a delay somewhere between reads would be too slow or too short. tWR & tRTP as main variables."
40	tWTR_L/SG	24
42
43	Interface Timings
44	CCD_S		8
45	CCD_L	=>tRRDL oder tRRDS	12
46	CCDL_WR	= CCDL *2	24
47
48	Mathematical Offset Timings
49	tRDRDSC_L min	5	CCDL	RdBurstChop	OdtEnDly
50	CCDL - RdBurstChop + ODTEnDly	5	12	8	1
51
52	tWRWRSC_L min	17	CCDLWR	WrBurstChop	OdtEnDly
53	CCDLWR - WrBurstChop + ODTEnDly	17	24	8	1
54
55	tRDWR min	16	tCL	tCWL	BurstChop	OdtEnDly	WrPRE (shown in MemTweak)	safety delay
56	tCL - tCWL + BC8 + ODTEnDly (1) + WrPRE + SafetyDly (1)	16	28	26	8	1	4	1
57
58	Tertiary Timings (SC + SD + DD)
59	If you have single sided Module, then you have to enter value 1 (for example 216 GB), if you have dual sided Modules (Chips on both sides like 232GB) you have to enter the value 0	1			_DD & _SD/DR	wenn 2x32bit MC/DIMM
60	tRDWR (lower 16 possible min formula above)	16			tCCD_S	4	not clear
61	tWRRD	1			tRDRD_	4	not clear
62	tRDRDSC	1			tWRWR_	3	not clear
63	tRDRDSD	1			tRDWR_	8	not clear
64	tRDRDDD	8			tWRRD_	2	not clear
65	tWRWRSC	1
66	tWRWRSD	1
67	tWRWRDD	6
68
69	tREFi < Maximum Value 65536(-1), please choose lower Value if you have thermal problems	65536	65536 (minus 8192 steps) = result -1 for BIOS input. // choose on thermal problems
70
71	tRRD_L/SG	16GB Dimm	24GB Dimm
72	tCCD_L Target is always equal to tCCD_S or higher.	8	12	CCDS , or bigger. CCDS is always 8 unless double MC link. Starting point 8+
73
74	Refresh Timings	tRFC
75	tRFC	429	you have to edit this value for calculate tRFC2+ tRFCsb at the moment AMD doesn't apply these values
76	tRFC2	233
77	tRFCsb	189
78
79	tWR Failsafe	tWR	tCL	tWTRL	Buffer 8
80	tWR = WTR_A+ RTP + X (BC8) ~ tCL+tWTRL+8	60	28	24	8
81	round up to multiple of 6	60
82
83
84	DDR5 VDD & VDDQ Voltage Delta Calculation
85	MEM VDD in Volt	1.55
86	Delta VDD & VDDQ in mVolt	90	60 mv should be safe more than 100 mv can be unstable for dual sided dimms According to specifications , max allowed is 300mV for in-mem delta.
87	MEM VDDQ in Volt	1.46
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