UCSD BGA Pad Rings (to substrate designer)

	A	B	C	D	E	F	G	H	I	J	K	L	M	N	O	P
1	Note: these PAD coordinates were approved by our bond house; I/Os should stay in the same position relative to the center of each chip edge. If you move them, you should get approval from the bond house.
2	Additional note: this is the official document used to transmit die coordinates to the substrate designer. Since then, for the bsg_one pinout, we have reversed the directions of sdo_A_sclk_i, sdo_B_sclk_i, sdo_C_sclk_i, sdo_D_sclk_i; so their names in all source code are sdo_A_sclk_o, sdo_B_sclk_o, sdo_C_sclk_o, sdo_D_sclk_o, and they are OUTPUT pins instead of input pins; hence they have suffix _o instead of _i. Note also: for bsg_two pinout, misc_L_3_i and misc_R_3_i have also been reversed in direction. Finally, pins 84 and 85 were swapped when we gave them to the designer, they have been updated to correct order here.
3			Adjusted X	Adjusted Y	Side	LL_X (micron)	LL_Y (micron)	UR_X (micron)	UR_Y (micron)	Original Name	Clk (Signal integrity)	Analog	Diff Pair	Relative Freq 500 if not noted	Match group

4	1	VSS	-2396.5	1930	0_LEFT	66	4397.5	141	4462.5	lt_0_i
5	2	V33	-2396.5	1805	0_LEFT	66	4272.5	141	4337.5	sdi_A_data_11_i
6	3	VSS	-2396.5	1680	0_LEFT	66	4147.5	141	4212.5	VSS_L_0
7	4	VDD	-2396.5	1600	0_LEFT	66	4067.5	141	4132.5	VDD_L_0
8	5	VSS	-2396.5	1520	0_LEFT	66	3987.5	141	4052.5	VSS_L_1
9	6	V33	-2396.5	1440	0_LEFT	66	3907.5	141	3972.5	V33_L_0
10	7	sdi_A_sclk_ex_i	-2281.5	1400	0_LEFT	181	3867.5	256	3932.5	sdi_A_tkn_ex_o	1			1000	Ai
11	8	VSS	-2396.5	1360	0_LEFT	66	3827.5	141	3892.5	VZZ_L_0
12	9	sdi_A_tkn_ex_o	-2281.5	1320	0_LEFT	181	3787.5	256	3852.5	sdi_A_data_8_i	1			1000	Ai
13	10	VDD	-2396.5	1280	0_LEFT	66	3747.5	141	3812.5	VDD_L_1
14	11	sdi_A_data_7_i	-2281.5	1240	0_LEFT	181	3707.5	256	3772.5	sdi_A_data_7_i					Ai
15	12	VSS	-2396.5	1200	0_LEFT	66	3667.5	141	3732.5	VSS_L_2
16	13	sdi_A_data_6_i	-2281.5	1160	0_LEFT	181	3627.5	256	3692.5	sdi_A_data_6_i					Ai
17	14	VDD	-2396.5	1120	0_LEFT	66	3587.5	141	3652.5	VDD_L_2
18	15	sdi_A_data_5_i	-2281.5	1080	0_LEFT	181	3547.5	256	3612.5	sdi_A_data_5_i					Ai
19	16	VSS	-2396.5	1040	0_LEFT	66	3507.5	141	3572.5	VSS_L_3
20	17	sdi_A_data_4_i	-2281.5	1000	0_LEFT	181	3467.5	256	3532.5	sdi_A_data_4_i					Ai
21	18	VDD	-2396.5	960	0_LEFT	66	3427.5	141	3492.5	VDD_L_3
22	19	sdi_A_data_3_i	-2281.5	920	0_LEFT	181	3387.5	256	3452.5	sdi_A_data_3_i					Ai
23	20	VSS	-2396.5	880	0_LEFT	66	3347.5	141	3412.5	VSS_L_4
24	21	misc_L_0_i	-2281.5	840	0_LEFT	181	3307.5	256	3372.5	misc_L_0_i
25	22	V33	-2396.5	800	0_LEFT	66	3267.5	141	3332.5	V33_L_1
26	23	sdi_A_token_o	-2281.5	760	0_LEFT	181	3227.5	256	3292.5	sdi_A_token_o	1			1000	Ai
27	24	VSS	-2396.5	720	0_LEFT	66	3187.5	141	3252.5	VZZ_L_1
28	25	misc_L_1_i	-2281.5	680	0_LEFT	181	3147.5	256	3212.5	misc_L_1_i
29	26	VDD	-2396.5	640	0_LEFT	66	3107.5	141	3172.5	VDD_L_4
30	27	sdi_A_sclk_i	-2281.5	600	0_LEFT	181	3067.5	256	3132.5	sdi_A_sclk_i	1			1000	Ai
31	28	VSS	-2396.5	560	0_LEFT	66	3027.5	141	3092.5	VSS_L_5
32	29	misc_L_2_i	-2281.5	520	0_LEFT	181	2987.5	256	3052.5	misc_L_2_i
33	30	VDD	-2396.5	480	0_LEFT	66	2947.5	141	3012.5	VDD_L_5
34	31	sdi_A_ncmd_i	-2281.5	440	0_LEFT	181	2907.5	256	2972.5	sdi_A_ncmd_i					Ai
35	32	VSS	-2396.5	400	0_LEFT	66	2867.5	141	2932.5	VSS_L_6
36	33	sdi_A_data_2_i	-2281.5	360	0_LEFT	181	2827.5	256	2892.5	sdi_A_data_2_i					Ai
37	34	VDD	-2396.5	320	0_LEFT	66	2787.5	141	2852.5	VDD_L_6
38	35	sdi_A_data_1_i	-2281.5	280	0_LEFT	181	2747.5	256	2812.5	sdi_A_data_1_i					Ai
39	36	VSS	-2396.5	240	0_LEFT	66	2707.5	141	2772.5	VSS_L_7
40	37	sdi_A_data_0_i	-2281.5	200	0_LEFT	181	2667.5	256	2732.5	sdi_A_data_0_i					Ai
41	38	V33	-2396.5	160	0_LEFT	66	2627.5	141	2692.5	V33_L_2
42	39	misc_L_3_i	-2281.5	120	0_LEFT	181	2587.5	256	2652.5	misc_L_3_i
43	40	VSS	-2396.5	80	0_LEFT	66	2547.5	141	2612.5	VZZ_L_2
44	41	clk_0_p_i	-2281.5	40	0_LEFT	181	2507.5	256	2572.5	clk_0_p_i	1		1	4000	Ki
45	42	VDD	-2396.5	0	0_LEFT	66	2467.5	141	2532.5	VDD_L_7
46	43	clk_0_n_i	-2281.5	-40	0_LEFT	181	2427.5	256	2492.5	clk_0_n_i	1		1	4000	Ki
47	44	VSS	-2396.5	-80	0_LEFT	66	2387.5	141	2452.5	VSS_L_8
48	45	misc_L_4_i	-2281.5	-120	0_LEFT	181	2347.5	256	2412.5	misc_L_4_i
49	46	VDD	-2396.5	-160	0_LEFT	66	2307.5	141	2372.5	VDD_L_8
50	47	sdi_B_data_0_i	-2281.5	-200	0_LEFT	181	2267.5	256	2332.5	sdi_B_data_0_i					Bi
51	48	VSS	-2396.5	-240	0_LEFT	66	2227.5	141	2292.5	VSS_L_9
52	49	sdi_B_data_1_i	-2281.5	-280	0_LEFT	181	2187.5	256	2252.5	sdi_B_data_1_i					Bi
53	50	VDD	-2396.5	-320	0_LEFT	66	2147.5	141	2212.5	VDD_L_9
54	51	sdi_B_data_2_i	-2281.5	-360	0_LEFT	181	2107.5	256	2172.5	sdi_B_data_2_i					Bi
55	52	VSS	-2396.5	-400	0_LEFT	66	2067.5	141	2132.5	VSS_L_10
56	53	sdi_B_data_3_i	-2281.5	-440	0_LEFT	181	2027.5	256	2092.5	sdi_B_data_3_i					Bi
57	54	VDD	-2396.5	-480	0_LEFT	66	1987.5	141	2052.5	VDD_L_10
58	55	sdi_B_ncmd_i	-2281.5	-520	0_LEFT	181	1947.5	256	2012.5	sdi_B_data_4_i					Bi
59	56	VSS	-2396.5	-560	0_LEFT	66	1907.5	141	1972.5	VSS_L_11
60	57	misc_L_5_i	-2281.5	-600	0_LEFT	181	1867.5	256	1932.5	misc_L_5_i
61	58	V33	-2396.5	-640	0_LEFT	66	1827.5	141	1892.5	V33_L_3
62	59	sdi_B_token_o	-2281.5	-680	0_LEFT	181	1787.5	256	1852.5	sdi_B_token_o	1			1000	Bi
63	60	VSS	-2396.5	-720	0_LEFT	66	1747.5	141	1812.5	VZZ_L_3
64	61	misc_L_6_i	-2281.5	-760	0_LEFT	181	1707.5	256	1772.5	misc_L_6_i
65	62	VDD	-2396.5	-800	0_LEFT	66	1667.5	141	1732.5	VDD_L_11
66	63	sdi_B_sclk_i	-2281.5	-840	0_LEFT	181	1627.5	256	1692.5	sdi_B_sclk_i	1			1000	Bi
67	64	VSS	-2396.5	-880	0_LEFT	66	1587.5	141	1652.5	VSS_L_12
68	65	misc_L_7_i	-2281.5	-920	0_LEFT	181	1547.5	256	1612.5	misc_L_7_i
69	66	VDD	-2396.5	-960	0_LEFT	66	1507.5	141	1572.5	VDD_L_12
70	67	sdi_B_data_4_i	-2281.5	-1000	0_LEFT	181	1467.5	256	1532.5	sdi_B_ncmd_i					Bi
71	68	VSS	-2396.5	-1040	0_LEFT	66	1427.5	141	1492.5	VSS_L_13
72	69	sdi_B_data_5_i	-2281.5	-1080	0_LEFT	181	1387.5	256	1452.5	sdi_B_data_5_i					Bi
73	70	VDD	-2396.5	-1120	0_LEFT	66	1347.5	141	1412.5	VDD_L_13
74	71	sdi_B_data_6_i	-2281.5	-1160	0_LEFT	181	1307.5	256	1372.5	sdi_B_data_6_i					Bi
75	72	VSS	-2396.5	-1200	0_LEFT	66	1267.5	141	1332.5	VSS_L_14
76	73	sdi_B_data_7_i	-2281.5	-1240	0_LEFT	181	1227.5	256	1292.5	sdi_B_data_7_i					Bi
77	74	V33	-2396.5	-1280	0_LEFT	66	1187.5	141	1252.5	V33_L_4
78	75	sdi_B_tkn_ex_o	-2281.5	-1320	0_LEFT	181	1147.5	256	1212.5	sdi_B_data_8_i	1			1000	Bi
79	76	VSS	-2396.5	-1360	0_LEFT	66	1107.5	141	1172.5	VZZ_L_4
80	77	sdi_B_sclk_ex_i	-2281.5	-1400	0_LEFT	181	1067.5	256	1132.5	sdi_B_tkn_ex_o	1			1000	Bi
81	78	VDD	-2396.5	-1440	0_LEFT	66	1027.5	141	1092.5	VDD_L_14
82	79	VSS	-2396.5	-1520	0_LEFT	66	947.5	141	1012.5	VSS_L_15
83	80	VDD	-2396.5	-1600	0_LEFT	66	867.5	141	932.5	VDD_L_15
84	81	VSS	-2396.5	-1680	0_LEFT	66	787.5	141	852.5	VSS_L_16
85	82	V33	-2396.5	-1805	0_LEFT	66	662.5	141	727.5	sdi_B_data_11_i					Bi
86	83	VSS	-2396.5	-1930	0_LEFT	66	537.5	141	602.5	lb_0_i
87	84	V33	-1950	-2396.5	1_BOTTOM	517.5	66	582.5	141	bl_0_i						was specified as VSS to substrate designer; fixed to V33 in 2017 and updated here.
88	85	VSS	-1825	-2396.5	1_BOTTOM	642.5	66	707.5	141	sdo_C_tkn_ex_i					Co	was specified as V33 to substrate designer; fixed to VSS in 2017 and updated here.
89	86	VDD	-1700	-2396.5	1_BOTTOM	767.5	66	832.5	141	VDD_B_0
90	87	VSS	-1620	-2396.5	1_BOTTOM	847.5	66	912.5	141	VSS_B_0
91	88	V33	-1540	-2396.5	1_BOTTOM	927.5	66	992.5	141	V33_B_0
92	89	VSS	-1460	-2396.5	1_BOTTOM	1007.5	66	1072.5	141	VZZ_B_0
93	90	sdo_C_tkn_ex_i	-1420	-2281.5	1_BOTTOM	1047.5	181	1112.5	256	sdo_C_data_9_o	1			1000	Co
94	91	VDD	-1380	-2396.5	1_BOTTOM	1087.5	66	1152.5	141	VDD_B_1
95	92	sdo_C_sclk_ex_o	-1340	-2281.5	1_BOTTOM	1127.5	181	1192.5	256	sdo_C_sclk_ex_o	1			1000	Co
96	93	VSS	-1300	-2396.5	1_BOTTOM	1167.5	66	1232.5	141	VSS_B_1
97	94	sdo_C_data_8_o	-1260	-2281.5	1_BOTTOM	1207.5	181	1272.5	256	sdo_C_data_8_o					Co
98	95	V33	-1220	-2396.5	1_BOTTOM	1247.5	66	1312.5	141	V33_B_1
99	96	sdo_C_data_7_o	-1180	-2281.5	1_BOTTOM	1287.5	181	1352.5	256	sdo_C_data_7_o					Co
100	97	VSS	-1140	-2396.5	1_BOTTOM	1327.5	66	1392.5	141	VZZ_B_1