Cache Coherence exercise Section 2

	A	B	C	D	E	F	G	H	I
1	Message (find addr or invalidate addr)	Memory bus addr? or addr=value			Address	State (M/S/I)	Value

2	10: find 1234			CPU 0 (Isaiah)	1234	I		&lock = 1234	struct lock { int locked; };
3		1234?	0
4	10: invalidate 1234			CPU 1 (name)					acquire(l) {
5	0: find 1234								while(true) {
6		1234 = 1		CPU 2 (name)					if(!xchg(&l->locked, 1))
7		1234?	1						break;
8	0: invalidate 1234			CPU 3 (Alex Bishka)	1234	M	1		}
9	7: find 1234								}
10		1234 =1		CPU 4 (name)
11		1234?	1						release(l) {
12	7: invalidate 1234			CPU 5 (Kevin)	1234	I			l->locked = 0;
13	5: find 1234								}
14		1234=1		CPU 6 (Marc)
15		1234?	1
16	5: invalidate 1234			CPU 7 (Thomas)
17	10: invalidate 1234				1234	I
18	3: find 1234			CPU 8 (Qualan)
19		1234=0
20		1234?	0	CPU 9 (name)
21	3: invalidate 1234
22				CPU 10 (Alex N)	1234	I
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