Analysis and Design of Elementary MOS Amplifier Stages: Errata
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Page Number and LocationOriginalNewNotes
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p. 8, left column, second line of algebraR_L/(R_L + R_out)R_out/(R_L + R_out)
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p. 8, third paragraphThis is illustrated through the circuit of Figure 1-10This is illustrated through the circuit of Figure 1-11
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p. 13, second column, A'_i, Two-Port expressionNeeds a negative sign (due to A_i = -1).
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p. 14, first column, A'_i, Exact expressionNeeds a negative sign.
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p. 17, P1.5The problem is unneccesarily complex with ri, ro, r1 and r2 included. The problem should be worked with ri, ro removed and r1=r2=0. Also, the following note should be added to part (a): Note that since this circuit is bilateral, RS must be considered when computing Rout, and RL must be considered when computing Rin.
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p. 17, P1.8The problem statement is missing values for RS and RL. Use RS=RL=10k. Also, Aif and Air are equal, so the conclusion must be drawn bassed on Rin and Rout.
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p.20, second column, equation 2.1I_D(y) = W*Q_n(y)*v(y)I_D = -W*Q_n(y)*v(y)I_D is constant throughout the channel (no dependence on y). Since I_D is defined as flowing into the drain, its mathematical definition in equation 2.1 requires a negative sign. The original right side of equation 2.1 shows the current flowing in the positive y direction, which is opposite the direction of I_D.
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p. 20, second column, last paragraphE(y) = dV(y)/dyE(y) = -dV(y)/dy
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p. 21, figure 2-3 (d)Q_n(L- L) = 0Q_n(L - deltaL) = 0
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p. 21, second column, line after equation 2.7for V_DS = V_GS - V_Tnfor V_DS >= V_GS - V_Tn
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p. 36, second column, second paragraph[e.g., a calculation of g_m using Eq. (2.23)][e.g., a calculation of g_m using Eq. (2.34)]
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p. 37, figure 2-16 legendEq. (3.29)Eq. (2.31)
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p. 42, Figure 2-22The v_out sinusoid should be phase shifted by 180 degrees for consistency with the inverting gain of the common-source stage.
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p. 49, P2.6This problem is obsolete, since it is already solved on page 31.
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p. 49, P2.7uCoxW/L = 100 A/V^2.5uCoxW/L = 100 uA/V^2.5
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p.50, P2.12Assume that VB=VDD/2Assume that VIN=VDD/2
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p.50, P2.14(a) calculate VBIAS(a) calculate VINAlso: VDD=5V should be given.
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p. 51, P2.17(b) Use the approximate approach from Example 2-7. (d) Repeat parts (a) and (b) without considering the connected RL. Explain the main differences in your answwers. Will these differences have an effect on the function of the amplifier? Distinguish between small- and large-signal characteristics of the the amplifier. (b) Take VDS dependence into account. (d) Repeat parts (a) and (b) without considering the connected RL and re-compute the two-port parameters of part (c). Summaríze the observed differences.
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p. 54, Bode magnitude plot1/omega1/(omega*RC)
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p. 58, phase plot of H(j*omega)H(j*omega)<H(j*omega)Missing phase label on y-axis
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p. 67, Fig 3-13bv_i/R_Sv_s/R_s
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p. 69, Eq. 3.441/p_2 >> 1/p_21/p_1 >> 1/p_2
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p. 71, left column, first paragraphexamining the voltages and currents of the capacitor C in Figure 3-16examining the voltages and currents of the capacitor C in Figure 3-15
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p. 75, top of left columnsubstituting Eq. (3.64) into Eq. (3.65)substituting Eq. (3.65) into Eq. (3.64)
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p. 81, P3.7V_B = 2VV_S = 2V
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p. 81, P3.8Examples 3-7 and 3-8Example 3-7Change for both occurences.
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p. 82, P3.15Rs = 10k, RD = 5kRs = 2RDThe values for RS and RD cannot be specified, but follow from the optimum point.
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p. 82, P3.15part (C): Also calculate the device width and drain currentAlso calculate RD, the device width and drain current
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p. 83, P3.16Rgd = RG + RS + Gm*RG*RSRgd = RG + RD + Gm*RG*RD
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p. 87A_well = (W+2X1) x (L+2L_diff+2X1+X2)A_well = (W+2X1) x (L+3L_diff+2X1+X2)The length of the well contact should be included by adding another L_diff. This should also be shown in Figure Ex4-1
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p. 88, Eq. 4.5di_D/dv_SBdi_D/dv_BS
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p. 92, Eq. 4.12delete extra "V" after the square root expression
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p. 92, Solution of Ex. 4-3Also: the equation under "we evaluate Eq. (4.12)..." does not belong here.
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p. 96, Eq. 4.25R_D || sC_DR_D || 1/sC_D
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p. 96, 8th line of second columnThis is simply RinThis is simply Rout
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p. 97, Eq. 4.29(1 + s[R_D||R_L])(C_d + C_L)1 + s([R_D||R_L][C_d + C_L])
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p. 98, Solution of Ex. 4-4Csb = 54.3fF, Cdb = 37.1fF, Cs = 257.6fF, Cd = 87.1fF, tau_so = 107ps, tau_do=261ps, f3dB = 432MHz.Csb = 19.6fF, Cdb = 13.4fF, Cs = 223fF, Cd = 63.4fF, tau_so = 92.25ps, tau_do=190.2ps, f3dB = 563MHz.
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p. 98, beginning of section 4-4-1using Eq. (4.13)using Eq. (4.12)
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p. 103, Ex. 4-6RS=10kRS=5kThe numbers computed in the example correspond to RS=5k.
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p. 105Approximating gm' ~ gm'Approximating gm' ~ gm
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p. 105gm' in (4.45) should be replaced with gm on all occurences (per the stated approximation)
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p. 109, Table 4-2, CG columnA_i = 1A_i = -1According the the diagram in Fig 4-30.
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p. 109, Table 4-2, CG columnr_o*(1 + g_m * r_s)r_o*(1 + g_m' * r_s)Should use g_m prime since it's used in the input resistance.
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p. 110, P4.2Repeat Example 4-3 assuming...Repeat Example 4-3 using IB = 200uA and assuming...
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p. 110, P4.3Several issues: 1) the resistance at the drain should be 5k. 2) The problem should be forst solved for the case of VSB=0 (part a), and then the gain should be recomputed witthe bulk connected to the supply (part b). 2) The propblem stament should include: The circuit is biased such that no DC current flows into the resistor connected to the drain. Explain why channel-length modulation can be safely neglected in the calculation of iout/is.
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p. 110, Figure P4-5IBIASIB
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p. 115, Table 5-2Rpoly = 40, 50, 60Rppoly = 60, 50, 40
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p. 117, first column, third pararaphFor instance, the nominal threshold voltage for n-channel transistors can vary by +/- 200VFor instance, the nominal threshold voltage for n-channel transistors can vary by +/- 200mV
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p. 120, Figure 5-4 and p. 121, Figure 5-5delta W is labelled as just W, missing the delta character
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p. 123, equation 5.13The numerators should be (u_n*Cox)_2 and the denominators (u_n*Cox)_1
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p. 124, Example 5-3in order to meet the compliance voltage requirement, we need V_GS = V_SG <= 1.5Vin order to meet the compliance voltage requirement, we need V_GS = V_SG <= 1VCompliance voltage = 0.5V = V_ov, V_T0n = abs(V_T0p) = 0.5V
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p. 125, second column, second paragraphr_s -> r_o2, r_o -> r_o1r_s -> r_o1, r_o -> r_o2
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p. 128, second column, first paragraphThe key idea in this setup is that M_4The key idea in this setup is that M_6
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p. 129, Table 5-5If k is the ratio W_2/W_6, the k values in the right column need to be inverted. The caption should say Figure 5-16.
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p. 129The final circuit of Figure 5-15(b)The final circuit of Figure 5-16(b)
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p. 131we know from Table 5-5we know from Table 5-6
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p. 133, Figure 5.20 and 5.21M1 and M2 labels need to be interchanged
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p. 134, footnotesource node of M2source node of M1
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p. 138, first column, second paragraphif the threshold voltage of M2 in Figure 5-25if the threshold voltage of M2 in figure 5-25(b)
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p. 140, P5.7Verify that the intersect wiht line (ii) corresponds to the current level given in Eq. (5.34).Verify graphically that the intersect with line (ii) corresponds to the current level given in Eq. (5.33). Assume the following parameters: m=4, W/L=25, R=2kOhm. Be sure to negelct channel-length modulation and backgate effect.
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p. 141, P5.11Missing information: Iref = 200uA, W/L = 50.
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p. 141, P5.12Assume VDD=5V.
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p. 141, P5.13VDS6=VDS7=VOV8VDS8=VDS7=VOV6
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p. 147, figure Ex6-1BCD dependent generator is drawn as a current source, should be a voltage source
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p. 147, end of Example 6-1Note that the output resistance and transresistance of the CG-CD configuration are lower than the CG-CS configuration by g_m2 * r_o2Note that the output resistance and transresistance of the CG-CD configuration are lower than those of the CG-CS configuration by g_m2 * R_D2
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p. 149, Example 6-2C_d1C_x
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p. 150, Figure Ex6-3C_d1C_x
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p. 150, Figure Ex6-3A_v2'A_v20'
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p. 150, Eq. 6.7C_d1C_x
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p. 152, Eq. 6.12C_d2sC_d2
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p. 153, Example 6-4In the calculation of tau_xo, the numerator should be gm+gmb, not gm.
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p. 154, end of first columnAn expression for the second pole frequency was derived in Eq. (3.56)An expression for the second pole frequency was derived in Eq. (3.59)
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p. 154, top of second columng_m2/C_gg2g_m2/C_gs2
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p. 157...set via the replica device M2...set via the replica device M2a
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p. 159, Eq. 6.21Missing R_D2 * C_gd2 term in tau_core
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p. 154, P6.3 and P6.4RL should be AC coupled with a large capacitance so that it does not affect the DC bias point of the circuit.
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p. 164, P6.5You are given the voltage amplifier shown in Figure P6-5 with (W/L)1 = 20 and (W/L)3 = 50. In this problem we will assume (for simplicity) that all backgates are shorted to their respective source terminals. Neglect channel-length modulation.You are given the voltage amplifier shown in Figure P6-5 with (W/L)1 = 20, (W/L)3 = 50, and all channel legths are equal to 1um. In this problem we will assume (for simplicity) that all backgates are shorted to their respective source terminals. Neglect channel-length modulation unless otherwsie stated.
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p. 164, P6.5(d) Draw a two-port model of this CS-CD stage and calculate the parameters.(d) Draw a two-port model of this CS-CD stage and calculate the parameters. Include the effect of channel-length modulation for M1 and M2.
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p. 166, P6.12W/L=4W/L=40Also: assume that W3 has the same width as all other transistors.
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