| A | B | C | D | |
|---|---|---|---|---|
1 | Cheatsheet | 1usmus_V3 | ||
2 | ||||
3 | TM5 Errors Decyphered | SOURCE | ||
4 | 1usmus_V3 | Error Type | Error Description | |
5 | ERROR #0 | RefreshStable 0Mb | Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Error 0 = BSOD 2,0,0,0,0 = not enough VDIMM 0,0,0,6,6,6 = too low SCL, bad tWRRD 0 at the start = overvoltage crash ^ also too high CkeDrvStr with too high procODT (only too high CkeDrvStr results in #6 solo) 0 bellow 5 cycles = too much VDIMM DDR5 - #0 spam with maybe #15's increase VPP_MEM (LDO) in'case this doesn't work, revert and increase VDDQ_CPU ↔ VDDQ_MEM delta | Veii (updated 20/01/2024) |
6 | ERROR #1 | Variable tests 16Mb | Can be voltage related, can be tRFC issues, Tiny timeout issues (tRRD, tWTR), can also be on the edge of stability CAD_BUS (depends if #6/#4 exist or not) | Veii |
7 | ERROR #2 | Variable tests 32Mb | Is a timeout issue, somewhere something ends too quickly or you lack voltage and cells are not recharged in time, a sync issue with other words, which's first culprit is voltage somewhere or resistance somewhere ^ needs updating and clearer findings - WIP Comes together with Voltages issues for #3, #4, #5, #8, #10, #14 Meaningless on it's own Supposedly too much RTT_PARK Not a definitive answer so far | Veii & BeCaReFuL24 (updated 10/11/2022) |
8 | ERROR #3 | MirrorMove 0Mb | Would suspect more tRDWR/tWRRD while for bigger dataset-errors before it = tRP, tRFC start with increasing tWTR_ , for example to 5-14 It can also be too low tRRD_L or too strong RTT_NOM | Veii (updated 23/09/2021) |
9 | ERROR #4 | MirrorMove128 0Mb | PCB Crash ! Too strong RTT values too high CAD_BUS ClkDrvStr wrong tCKE or too high VDIMM | Veii (updated 18/01/2021) |
10 | ERROR #5 | MirrorMove 0Mb | Would suspect more tRDWR/tWRRD while for bigger datasets tRP, tRFC - it can error after the 2nd or 3rd pass if something is off by some ns and just "got lost" Can be incorrect RTL training, or on AMD too high/low cLDO_VDDP & ClkDrvStr causing tPHYRDL missmatch | Veii & Bloax (updated 08/04/2022) |
11 | ERROR #6 | Random tests 1Mb | Is purely related to the IMC (Can mean voltage is too high) , be if procODT, CLDO_VDDP or vSOC ~ it translates to "i couldn't even start transfering data, i crashed" 4-6x error 6 result in full bluescreen - Error 5 then 6 is a timings missmatch between dimms (Data mirror move) 0-0-0-6-6-6 (2nd cycle) Can be too low SCL with wrong tWRRD Single rare 6 (after time), fix RTT values or give it +1 vDIMM 6-6-6 at the very start , too high/low tCKE * * start with this first | Veii (updated 01/12/2021) |
12 | ERROR #7 | MirrorMove 2Mb | It will error out if if CAD_BUS or CAD_BUS SETUP Time is not optimal (lower CkeSetup) will error out of tRFC is too low, mostly errors out only after time Suspect vDIMM to be +/- 1 step too high/low, tFAW be awkward value, or tRAS needing +1 1-7-7 or 7-1-8-8 (increase CkeDrvStr) | Veii (updated 05/04/2021) |
13 | ERROR #8 | Random tests 0Mb | =Error #1 1x #8 at the end = badly timed tWTR_ Likely too low tWTR_S Can also be too high tWTR_L , but first try higher tWTR_S | Veii (updated 23/09/2021) |
14 | ERROR #9 | MirrorMove 4Mb | Suspect tWR being too slow, voltage stability issue If you've lowered tRP , increase vDimm a tiny bit If you've increased tRP to longer delay, decrease vDIMM +0.01 , one tiny step | Veii |
15 | ERROR #10 | Random tests 8Mb | Suspect tWR being too slow (lower value required) mostly affects the first 5 main timings - noticed it can be tRCDWR to RD, can be tRP too, but it also can be the last two tRDWR & tWRRD which don't play well with your main tRCDWR/RD #10 at the very start = increase RTT_NOM to something stronger | Veii |
16 | ERROR #11 | Random tests 16Mb | It is most likely RAM overheating it will error out if if CAD_BUS is not optimal or SETUP Times are wrong will error out of tRFC is too low, mostly errors out only after time Suspect vDIMM to be +/- 1 step too high/low, tFAW be awkward value, or tRAS & tRTP needing +2 | Veii (corrected 02/27/2023) |
17 | ERROR #12 | Random tests 32Mb | = ERROR #2 If right at the start, increase procODT once, or make RTT_NOM stronger Also make CPU 1.8V line weaker Alternatively - weaken ClkDrvStr & increase VDIMM slightly | Veii (updated 21/01/2021) |
18 | ERROR #13 | Random tests 64Mb | It is most likely RAM overheating timeout while transfering big data - full crash, nearly always related to too much voltage or bad SNR by RTTs Explosion of #13's, - try to lower VDIMM or use a stronger RTT_NOM probably both Random #13's, still in the first loop: increase procODT (weaker) | Veii & PJVol (rephrased 21/01/2023) |
19 | ERROR #14 | MirrorMove 0Mb | 14 / 4 / 0 - relate to badly used CAD_BUS SETUP Timing Too low CAD_BUS AddrCmdDrvStr/CsOdtDrvStren/CkeDrvStren or overal badly timed powerdown They will appear together, because it's the dimms crashing on badly timed values 0,0,14,0, 9 = too much VDIMM | Veii (updated 01/01/2022) |
20 | ERROR #15 | MirrorMove128 0Mb | Crashed after #15 = End of one Cycle Timing accuracy related Can be everything from (tCWL≠tCL, tRFC, vDIMM, tFAW smaller than tRRD_L, too tight tRRD_) Can also be an unstable Curve Optimizer core - verify with y-cruncher first (1-7-0 - 4 loops = 72min) | Veii (added 01/12/2021) |