Flip Flops

	A	B	C	D	E	F	G	H	I	J	K	L	M	N	O	P	Q	R	S	T
1	Name	Support	Type	Class	Sync Async	Polarity					Init Values		Generated Name	Signal Names						Usage
2	Name	Support	Type	Class	Sync Async	Clock / Gate	Clock Enable / Gate Enable	Set	Reset	Reset Value	Set	Reset	Generated Name	Data In (D)	Clock (C) / Gate (G)	Clock Enable (CE) / Gate Enable (GE)	Set (S)	Reset (R)	Data Out (Q)	Usage

3	$_SR_NN_	Native	SR	Flip-flop	Async			Negative	Negative		1	0	NN				S	R	Q
4	$_SR_NP_	Native	SR	Flip-flop	Async			Negative	Positive		1	0	NP				S	R	Q
5	$_SR_PN_	Native	SR	Flip-flop	Async			Positive	Negative		1	0	PN				S	R	Q
6	$_SR_PP_	Native	SR	Flip-flop	Async			Positive	Positive		1	0	PP				S	R	Q
7	$_DFF_N_	Native	D	Flip-flop	Sync	Negative							N	D	C				Q
8	$_DFF_NN0_	Native	D	Flip-flop	Async	Negative			Negative	0		0	NN0	D	C			R	Q
9	$_DFF_NN1_	Native	D	Flip-flop	Async	Negative			Negative	1		1	NN1	D	C			R	Q
10	$_DFF_NP0_	Native	D	Flip-flop	Async	Negative			Positive	0		0	NP0	D	C			R	Q
11	$_DFF_NP1_	Native	D	Flip-flop	Async	Negative			Positive	1		1	NP1	D	C			R	Q
12	$__DFFS_NN0_	Special	D	Flip-flop	Sync	Negative			Negative	0		0	NN0	D	C			R	Q	ECP - dff2dffs
13	$__DFFS_NN1_	Special	D	Flip-flop	Sync	Negative			Negative	1		1	NN1	D	C			R	Q	ECP - dff2dffs
14	$__DFFS_NP0_	Special	D	Flip-flop	Sync	Negative			Positive	0		0	NP0	D	C			R	Q	ECP - dff2dffs
15	$__DFFS_NP1_	Special	D	Flip-flop	Sync	Negative			Positive	1		1	NP1	D	C			R	Q	ECP - dff2dffs
16	$_DFFE_NN_	Native	D	Flip-flop	Sync	Negative	Negative						NN	D	C	E			Q
17	$_DFFE_NP_	Native	D	Flip-flop	NA	Negative	Positive						NP	D	C	E			Q
18	$__DFFE_NN0	Special	D	Flip-flop	Async	Negative	Negative		Negative	0		0	NNN0	D	C	E		R	Q	None
19	$__DFFE_NN1	Special	D	Flip-flop	Async	Negative	Negative		Negative	1		1	NNN1	D	C	E		R	Q	None
20	$__DFFE_NP0	Special	D	Flip-flop	Async	Negative	Negative		Positive	0		0	NNP0	D	C	E		R	Q	None
21	$__DFFE_NP1	Special	D	Flip-flop	Async	Negative	Negative		Positive	1		1	NNP1	D	C	E		R	Q	None
22	$__DFFE_NN0	Special	D	Flip-flop	Async	Negative	Positive		Negative	0		0	NPN0	D	C	E		R	Q	ECP - dff2dffs
23	$__DFFE_NN1	Special	D	Flip-flop	Async	Negative	Positive		Negative	1		1	NPN1	D	C	E		R	Q	ECP - dff2dffs
24	$__DFFE_NP0	Special	D	Flip-flop	Async	Negative	Positive		Positive	0		0	NPP0	D	C	E		R	Q	ECP - dff2dffs
25	$__DFFE_NP1	Special	D	Flip-flop	Async	Negative	Positive		Positive	1		1	NPP1	D	C	E		R	Q	ECP - dff2dffs
26	$__DFFSE_NN0	Special	D	Flip-flop	Sync	Negative	Negative		Negative	0		0	NNN0	D	C	E		R	Q	None
27	$__DFFSE_NN1	Special	D	Flip-flop	Sync	Negative	Negative		Negative	1		1	NNN1	D	C	E		R	Q	None
28	$__DFFSE_NP0	Special	D	Flip-flop	Sync	Negative	Positive		Positive	0		0	NPP0	D	C	E		R	Q	None
29	$__DFFSE_NP1	Special	D	Flip-flop	Sync	Negative	Positive		Positive	1		1	NPP1	D	C	E		R	Q	None
30	$__DFFSE_NN0	Special	D	Flip-flop	Sync	Negative	Negative		Negative	0		0	NNN0	D	C	E		R	Q	ECP - dff2dffs
31	$__DFFSE_NN1	Special	D	Flip-flop	Sync	Negative	Negative		Negative	1		1	NNN1	D	C	E		R	Q	ECP - dff2dffs
32	$__DFFSE_NP0	Special	D	Flip-flop	Sync	Negative	Positive		Positive	0		0	NPP0	D	C	E		R	Q	ECP - dff2dffs
33	$__DFFSE_NP1	Special	D	Flip-flop	Sync	Negative	Positive		Positive	1		1	NPP1	D	C	E		R	Q	ECP - dff2dffs
34	$_DFFSR_NNN_	Native	D	Flip-flop	Async	Negative		Negative	Negative		1	0	NNN	D	C		S	R	Q
35	$_DFFSR_NNP_	Native	D	Flip-flop	Async	Negative		Negative	Positive		1	0	NNP	D	C		S	R	Q
36	$_DFFSR_NPN_	Native	D	Flip-flop	Async	Negative		Positive	Negative		1	0	NPN	D	C		S	R	Q
37	$_DFFSR_NPP_	Native	D	Flip-flop	Async	Negative		Positive	Positive		1	0	NPP	D	C		S	R	Q
38	$_DFF_P_	Native	D	Flip-flop	NA	Positive							P	D	C				Q
39	$_DFF_PN0_	Native	D	Flip-flop	Async	Positive			Negative	0		0	PN0	D	C			R	Q
40	$_DFF_PN1_	Native	D	Flip-flop	Async	Positive			Negative	1		1	PN1	D	C			R	Q
41	$_DFF_PP0_	Native	D	Flip-flop	Async	Positive			Positive	0		0	PP0	D	C			R	Q
42	$_DFF_PP1_	Native	D	Flip-flop	Async	Positive			Positive	1		1	PP1	D	C			R	Q
43	$__DFFS_PN0_	Special	D	Flip-flop	Sync	Positive			Negative	0		0	PN0	D	C			R	Q	ECP - dff2dffs
44	$__DFFS_PN1_	Special	D	Flip-flop	Sync	Positive			Negative	1		1	PN1	D	C			R	Q	ECP - dff2dffs
45	$__DFFS_PP0_	Special	D	Flip-flop	Sync	Positive			Positive	0		0	PP0	D	C			R	Q	ECP - dff2dffs
46	$__DFFS_PP1_	Special	D	Flip-flop	Sync	Positive			Positive	1		1	PP1	D	C			R	Q	ECP - dff2dffs
47	$_DFFE_PN_	Native	D	Flip-flop	NA	Positive	Negative						PN	D	C	E			Q
48	$_DFFE_PP_	Native	D	Flip-flop	NA	Positive	Positive						PP	D	C	E			Q
49	$__DFFE_PN0	Special	D	Flip-flop	Async	Positive	Negative		Negative	0		0	PNN0	D	C	E		R	Q	None
50	$__DFFE_PN1	Special	D	Flip-flop	Async	Positive	Negative		Negative	1		1	PNN1	D	C	E		R	Q	None
51	$__DFFE_PP0	Special	D	Flip-flop	Async	Positive	Positive		Positive	0		0	PPP0	D	C	E		R	Q	None
52	$__DFFE_PP1	Special	D	Flip-flop	Async	Positive	Positive		Positive	1		1	PPP1	D	C	E		R	Q	None
53	$__DFFE_PN0	Special	D	Flip-flop	Async	Positive	Negative		Negative	0		0	PNN0	D	C	E		R	Q	ECP - dff2dffs
54	$__DFFE_PN1	Special	D	Flip-flop	Async	Positive	Negative		Negative	1		1	PNN1	D	C	E		R	Q	ECP - dff2dffs
55	$__DFFE_PP0	Special	D	Flip-flop	Async	Positive	Positive		Positive	0		0	PPP0	D	C	E		R	Q	ECP - dff2dffs
56	$__DFFE_PP1	Special	D	Flip-flop	Async	Positive	Positive		Positive	1		1	PPP1	D	C	E		R	Q	ECP - dff2dffs
57	$__DFFSE_PN0	Special	D	Flip-flop	Sync	Positive	Negative		Negative	0		0	PNN0	D	C	E		R	Q	None
58	$__DFFSE_PN1	Special	D	Flip-flop	Sync	Positive	Negative		Negative	1		1	PNN1	D	C	E		R	Q	None
59	$__DFFSE_PP0	Special	D	Flip-flop	Sync	Positive	Positive		Positive	0		0	PPP0	D	C	E		R	Q	None
60	$__DFFSE_PP1	Special	D	Flip-flop	Sync	Positive	Positive		Positive	1		1	PPP1	D	C	E		R	Q	None
61	$__DFFSE_PN0	Special	D	Flip-flop	Sync	Positive	Negative		Negative	0		0	PNN0	D	C	E		R	Q	ECP - dff2dffs
62	$__DFFSE_PN1	Special	D	Flip-flop	Sync	Positive	Negative		Negative	1		1	PNN1	D	C	E		R	Q	ECP - dff2dffs
63	$__DFFSE_PP0	Special	D	Flip-flop	Sync	Positive	Positive		Positive	0		0	PPP0	D	C	E		R	Q	ECP - dff2dffs
64	$__DFFSE_PP1	Special	D	Flip-flop	Sync	Positive	Positive		Positive	1		1	PPP1	D	C	E		R	Q	ECP - dff2dffs
65	$_DFFSR_PNN_	Native	D	Flip-flop	Async	Positive		Negative	Negative		1	0	PNN	D	C		S	R	Q
66	$_DFFSR_PNP_	Native	D	Flip-flop	Async	Positive		Negative	Positive		1	0	PNP	D	C		S	R	Q
67	$_DFFSR_PPN_	Native	D	Flip-flop	Async	Positive		Positive	Negative		1	0	PPN	D	C		S	R	Q
68	$_DFFSR_PPP_	Native	D	Flip-flop	Async	Positive		Positive	Positive		1	0	PPP	D	C		S	R	Q
69	$_DLATCH_N_	Native	D	Latch	Async	Negative							N	D	E				Q
70	$_DLATCHSR_NNN_	Native	D	Latch	Async	Negative		Negative	Negative		1	0	NNN	D	E		S	R	Q
71	$_DLATCHSR_NNP_	Native	D	Latch	Async	Negative		Negative	Positive		1	0	NNP	D	E		S	R	Q
72	$_DLATCHSR_NPN_	Native	D	Latch	Async	Negative		Positive	Negative		1	0	NPN	D	E		S	R	Q
73	$_DLATCHSR_NPP_	Native	D	Latch	Async	Negative		Positive	Positive		1	0	NPP	D	E		S	R	Q
74	$_DLATCH_P_	Native	D	Latch	Async	Positive							P	D	E				Q
75	$_DLATCHSR_PNN_	Native	D	Latch	Async	Positive		Negative	Negative		1	0	PNN	D	E		S	R	Q
76	$_DLATCHSR_PNP_	Native	D	Latch	Async	Positive		Negative	Positive		1	0	PNP	D	E		S	R	Q
77	$_DLATCHSR_PPN_	Native	D	Latch	Async	Positive		Positive	Negative		1	0	PPN	D	E		S	R	Q
78	$_DLATCHSR_PPP_	Native	D	Latch	Async	Positive		Positive	Positive		1	0	PPP	D	E		S	R	Q
79	$_FF_	Native	D	Flip-flop	Sync	Implicit							I	D					Q