Tim's Open FPGA Expansion (TOFE) board connector interface
Comments
 Share
The version of the browser you are using is no longer supported. Please upgrade to a supported browser.Dismiss

 
Comment only
 
 
Still loading...
ABCDEFGHIJKLMNOPQRSTUVWX
1
DescriptionDescriptionSpeed Ratings (x samples / second)"Super High Speed" Config - 4x"High Speed" Config - 1xNon-GTP Config - 4xNon-GTP Config - 8xNon-GTP Config - 16x
2
PinSide BSide ASide BSide ASide BSide ASide BSide ASide BSide ASide BSide ASide BSide A
3
1+12 VPRSNT1#12V PowerBoard size identification+12 VPRSNT1#+12 VPRSNT1#+12 VPRSNT1#+12 VPRSNT1#+12 VPRSNT1#
4
2+12 V+12 V12V Power+12 V+12 V+12 V+12 V+12 V+12 V+12 V+12 V+12 V+12 V
5
3+12 V+12 V12V Power+12 V+12 V+12 V+12 V+12 V+12 V+12 V+12 V+12 V+12 V
6
4GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
7
5SMCLKDIFF IO A 0PExpansion board identification and configurationDiff IO pair A0Max 10 M/sMax 1.5G/sSMCLKDIFF IO A 0PSMCLKDIFF IO A 0PSMCLKDIFF IO A 0PSMCLKDIFF IO A 0PSMCLKDIFF IO A 0P
8
6SMDATDIFF IO A 0NMax 10 M/sSMDATDIFF IO A 0NSMDATDIFF IO A 0NSMDATDIFF IO A 0NSMDATDIFF IO A 0NSMDATDIFF IO A 0N
9
7GNDDIFF IO B 0PDiff IO pair B03.3V PowerMax 1.5G/sGNDDIFF IO B 0PGNDDIFF IO B 0PGNDDIFF IO B 0PGNDDIFF IO B 0PGNDDIFF IO B 0P
10
8+3.3 VDIFF IO B 0N3.3V Power+3.3 VDIFF IO B 0N+3.3 VDIFF IO B 0N+3.3 VDIFF IO B 0N+3.3 VDIFF IO B 0N+3.3 VDIFF IO B 0N
11
9DIFF IO XP+3.3 VSpecial Diff IO pair X (+)3.3V PowerMax 500M/sDIFF IO XP+3.3 VDIFF IO XP+3.3 VDIFF IO XP+3.3 VDIFF IO XP+3.3 VDIFF IO XP+3.3 V
12
10+3.3 V aux+3.3 V3.3V Power3.3V Power+3.3 V aux+3.3 V+3.3 V aux+3.3 V+3.3 V aux+3.3 V+3.3 V aux+3.3 V+3.3 V aux+3.3 V
13
11DIFF IO XNPERST#Special Diff IO pair X (-)Expansion board resetMax 500M/sDIFF IO XNPERST#DIFF IO XNPERST#DIFF IO XNPERST#DIFF IO XNPERST#DIFF IO XNPERST#
14
11.5Keynotch
15
12DIFF IO YNGNDSpecial Diff IO pair Y (-)Max 500M/sDIFF IO YNGNDIOGNDDIFF IO YNGNDDIFF IO YNGNDDIFF IO YNGND
16
13GNDDIFF GCLK XPSpecial Diff Clock pair XMax 10G/s
(or)
Max 1.5G/s
GND
MGTREFCLK0N_101
GNDDIFF GCLK XPGNDDIFF GCLK XPGNDDIFF GCLK XPGNDDIFF GCLK XP
17
14DIFF IO B 1PDIFF GCLK XNDiff IO pair B1Max 10G/s
(or)
Max 1.5G/s
MGTRXN0_101
MGTREFCLK0P_101
DIFF IO B 1PDIFF GCLK XNDIFF IO B 1PDIFF GCLK XNDIFF IO B 1PDIFF GCLK XNDIFF IO B 1PDIFF GCLK XN
18
15DIFF IO B 1NGNDMGTRXP0_101GNDDIFF IO B 1NGNDDIFF IO B 1NGNDDIFF IO B 1NGNDDIFF IO B 1NGND
19
16GNDDIFF IO A 1PDiff IO pair A0Max 10G/s
(or)
Max 1.5G/s
GNDMGTTXN0_101GNDDIFF IO A 1PGNDDIFF IO A 1PGNDDIFF IO A 1PGNDDIFF IO A 1P
20
17PRSNT2#DIFF IO A 1NBoard size identificationPRSNT2#MGTTXP0_101PRSNT2#DIFF IO A 1NPRSNT2#DIFF IO A 1NPRSNT2#DIFF IO A 1NPRSNT2#DIFF IO A 1N
21
18GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
22
18.5PCI Express ×1 cards end at pin 18---------------------------------------------
23
19DIFF IO B 2PDIFF IO YPDiff IO pair B2Special Diff IO pair Y (+)Max 10G/s
(or)
Max 1.5G/s
Max 500M/sMGTRXN1_101DIFF IO YPDIFF IO*10DIFF IO B 2PDIFF IO YPDIFF IO B 2PDIFF IO YPDIFF IO B 2PDIFF IO YP
24
20DIFF IO B 2NGNDMGTRXP1_101GNDDIFF GCLK*2DIFF IO B 2NGNDDIFF IO B 2NGNDDIFF IO B 2NGND
25
21GNDDIFF IO A 2PDiff IO pair A2Max 10G/s
(or)
Max 1.5G/s
GNDMGTTXN1_101IO1GNDDIFF IO A 2PGNDDIFF IO A 2PGNDDIFF IO A 2P
26
22GNDDIFF IO A 2NGNDMGTTXP1_101Total IO Pins13GNDDIFF IO A 2NGNDDIFF IO A 2NGNDDIFF IO A 2N
27
23DIFF IO B 3PGNDDiff IO pair B3Max 10G/s
(or)
Max 1.5G/s
MGTRXN0_123GNDDIFF IO B 3PGNDDIFF IO B 3PGNDDIFF IO B 3PGND
28
24DIFF IO B 3NGNDMGTRXP0_123GNDDIFF GCLK X*2DIFF IO B 3NGNDDIFF IO B 3NGNDDIFF IO B 3NGND
29
25GNDDIFF IO A 3PDiff IO pair A3Max 10G/s
(or)
Max 1.5G/s
GNDMGTTXN0_123DIFF GCLK 0*0GNDDIFF IO A 3PGNDDIFF IO A 3PGNDDIFF IO A 3P
30
26GNDDIFF IO A 3NGNDMGTTXP0_123Total Lanes1GNDDIFF IO A 3NGNDDIFF IO A 3NGNDDIFF IO A 3N
31
27DIFF GCLK 0P BGNDDiff Clock pair B0Max 10G/s
(or)
Max 1.5G/s
MGTRXN1_123GNDDIFF GCLK 0P BGNDDIFF GCLK 0P BGNDDIFF GCLK 0P BGND
32
28DIFF GCLK 0N BGNDMGTRXP1_123GNDDIFF IO X*2DIFF GCLK 0N BGNDDIFF GCLK 0N BGNDDIFF GCLK 0N BGND
33
29GNDDIFF GCLK 0P ADiff Clock pair A0Max 10G/s
(or)
Max 1.5G/s
GNDMGTTXN1_123DIFF IO Y*0GNDDIFF GCLK 0P AGNDDIFF GCLK 0P AGNDDIFF GCLK 0P A
34
30DIFF IO ZNDIFF GCLK 0P ASpecial Diff IO pair Z (-)Max 500M/sDIFF IO ZNMGTTXP1_123Total Lanes1DIFF IO ZNDIFF GCLK 0P ADIFF IO ZNDIFF GCLK 0P ADIFF IO ZNDIFF GCLK 0P A
35
31PRSNT2#GNDBoard size identificationPRSNT2#GNDPRSNT2#GNDPRSNT2#GNDPRSNT2#GND
36
32GNDDIFF IO ZPSpecial Diff IO pair Z (+)Max 500M/sGNDDIFF IO ZPDIFF IO *B*4GNDDIFF IO ZPGNDDIFF IO ZPGNDDIFF IO ZP
37
32.5PCI Express ×4 cards end at pin 32DIFF IO *A*4---------------------------------------------
38
33DIFF IO B 4PIO0Diff IO pair B4Spare IO PinMax 10G/s
(or)
Max 1.5G/s
DIFF IO*22DIFF IO B 4PIO0DIFF IO B 4PIO0
39
34DIFF IO B 4NGNDDIFF IO *0*4DIFF GCLK*6DIFF IO B 4NGNDDIFF IO B 4NGND
40
35GNDDIFF IO A 4PDiff IO pair A4Max 10G/s
(or)
Max 1.5G/s
DIFF IO *1*4IO0GNDDIFF IO A 4PGNDDIFF IO A 4P
41
36GNDDIFF IO A 4NDIFF IO *2*0Total IO Pins28GNDDIFF IO A 4NGNDDIFF IO A 4N
42
37DIFF IO B 5PGNDDiff IO pair B5Max 10G/s
(or)
Max 1.5G/s
Total Lanes4DIFF IO B 5PGNDDIFF IO B 5PGND
43
38DIFF IO B 5NGNDDIFF GCLK X*2DIFF IO B 5NGNDDIFF IO B 5NGND
44
39GNDDIFF IO A 5PDiff IO pair A5Max 10G/s
(or)
Max 1.5G/s
---------------------------------------------GNDDIFF IO A 5PGNDDIFF IO A 5P
45
40GNDDIFF IO A 5NDIFF GCLK 0*4GNDDIFF IO A 5NGNDDIFF IO A 5N
46
41DIFF IO B 6PGNDDiff IO pair B6Max 10G/s
(or)
Max 1.5G/s
DIFF GCLK 1*0DIFF IO B 6PGNDDIFF IO B 6PGND
47
42DIFF IO B 6NGNDTotal Lanes3DIFF IO B 6NGNDDIFF IO B 6NGND
48
43GNDDIFF IO A 6PDiff IO pair A6Max 10G/s
(or)
Max 1.5G/s
GNDDIFF IO A 6PGNDDIFF IO A 6P
49
44GNDDIFF IO A 6NDIFF IO X*2GNDDIFF IO A 6NGNDDIFF IO A 6N
50
45DIFF GCLK 1P BGNDDiff Clock pair B1Max 10G/s
(or)
Max 1.5G/s
---------------------------------------------DIFF GCLK 1P BGNDDIFF GCLK 1P BGND
51
46DIFF GCLK 1N BGNDDIFF IO Y*2DIFF GCLK 1N BGNDDIFF GCLK 1N BGND
52
47GNDDIFF GCLK 1P ADiff Clock pair A1Max 10G/s
(or)
Max 1.5G/s
DIFF IO Z*2GNDDIFF GCLK 1P AGNDDIFF GCLK 1P A
53
48PRSNT2#DIFF GCLK 1N ABoard size identificationTotal Lanes3PRSNT2#DIFF GCLK 1N APRSNT2#DIFF GCLK 1N A
54
49GNDGNDGNDGNDGNDGND
55
49.5PCI Express ×8 cards end at pin 49DIFF IO *B*8---------------------------------------------
56
50DIFF IO B 7PIO1Max 10G/s
(or)
Max 1.5G/s
Max 10 M/sDIFF IO *A*8DIFF IO*34DIFF IO B 7PIO1
57
51DIFF IO B 7NGNDDIFF GCLK*10DIFF IO B 7NGND
58
52GNDDIFF IO A 7PMax 10G/s
(or)
Max 1.5G/s
DIFF IO *0*4IO*1GNDDIFF IO A 7P
59
53GNDDIFF IO A 7NDIFF IO *1*4Total IO Pins45GNDDIFF IO A 7N
60
54DIFF IO B 8PGNDMax 10G/s
(or)
Max 1.5G/s
---------------------------------------------DIFF IO B 8PGND
61
55DIFF IO B 8NGNDDIFF IO *2*4DIFF GCLK X*2DIFF IO B 8NGND
62
56GNDDIFF IO A 8PMax 10G/s
(or)
Max 1.5G/s
DIFF IO *3*4DIFF GCLK *0*4GNDDIFF IO A 8P
63
57GNDDIFF IO A 8NDIFF IO *4*0---------------------------------------------GNDDIFF IO A 8N
64
58DIFF IO B 9PGNDMax 10G/s
(or)
Max 1.5G/s
Total Lanes8DIFF GCLK *1*4DIFF IO B 9PGND
65
59DIFF IO B 9NGNDDIFF GCLK *2*0DIFF IO B 9NGND
66
60GNDDIFF IO A 9PMax 10G/s
(or)
Max 1.5G/s
Total Lanes5GNDDIFF IO A 9P
67
61GNDDIFF IO A 9NGNDDIFF IO A 9N
68
62DIFF IO B 10PGNDMax 10G/s
(or)
Max 1.5G/s
DIFF IO X*2DIFF IO B 10PGND
69
63DIFF IO B 10NGNDDIFF IO Y*2DIFF IO B 10NGND
70
64GNDDIFF IO A 10PMax 10G/s
(or)
Max 1.5G/s
DIFF IO Z*2GNDDIFF IO A 10P
71
65GNDDIFF IO A 10NTotal Lanes3GNDDIFF IO A 10N
72
66DIFF IO B 11PGNDMax 10G/s
(or)
Max 1.5G/s
DIFF IO B 11PGND
73
67DIFF IO B 11NGNDDIFF IO *B*14DIFF IO B 11NGND
74
68GNDDIFF IO A 11PMax 10G/s
(or)
Max 1.5G/s
DIFF IO *A*14GNDDIFF IO A 11P
75
69GNDDIFF IO A 11NGNDDIFF IO A 11N
76
70DIFF GCLK 2P BGNDMax 10G/s
(or)
Max 1.5G/s
DIFF IO *0*4DIFF GCLK 2P BGND
77
71DIFF GCLK 2N BGNDDIFF IO *1*4DIFF GCLK 2N BGND
78
72GNDDIFF GCLK 2P AMax 10G/s
(or)
Max 1.5G/s
DIFF IO *2*4GNDDIFF GCLK 2P A
79
73GNDDIFF GCLK 2N ADIFF IO *3*4GNDDIFF GCLK 2N A
80
74IO2GNDMax 500M/sDIFF IO *4*4IO2GND
81
75IO3GNDMax 500M/s---------------------------------------------IO3GND
82
76GNDIO4Max 500M/sDIFF IO *5*4GNDIO4
83
77GNDIO5Max 500M/sDIFF IO *6*4GNDIO5
84
78IO6GNDMax 500M/sDIFF IO *7*0IO6GND
85
79IO7GNDMax 500M/sTotal Lanes14IO7GND
86
80GNDIO8Max 500M/sGNDIO8
87
81PRSNT2#IO9Max 500M/sPRSNT2#IO9
88
82IO10GNDMax 500M/sIO10GND
89
PCI Express ×16 cards end at pin 82---------------------------------------------
90
DIFF IO *54DIFF IO0
91
DIFF GCLK *14DIFF GCLK0
92
IO*11IO*11
93
GCLK0GCLK0
94
NC0NC0
95
Total IO Pins79Total IO Pins11
96
97
DIFF GCLK X*2DIFF GCLK X*2
98
DIFF GCLK *0*4DIFF GCLK *0*4
99
DIFF GCLK *1*4DIFF GCLK *1*4
100
------------------------------------------------------------------------------------------
Loading...
 
 
 
Expansion Card Interface
Configs
TOFE Hosts
TOFE to Display Tech
TODO: TOFE HiLink
TOFE to apertus°
TOFE to Atlys VHDCI
TOFE to Altera HSMC
|| Pin Analysis -->
Pin Counts - Connectors
Pins Needed - Interfaces
|| Existing Specs -->
PCIE - Summary Sheet
PCIE - Pin Counts
Altera HSMC - Diff Spec
Digilent VHDCI Connector "Spec"
apertus° - open source cinema
PCIE - Basic Structures
DP++ Pin Usage