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DDR5 Timing Calculator for AMD by RedF & Wolf87, Guided by Veii
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Version 0.0.08
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Primary Timingsuse this formula at your own riskcalculatedEditdo not touch !
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tCL28
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tRCDWR37
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tRCDRD37
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tRP37
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tRTP12
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tWR48tWR Rule is not under 48, but 24 is somewhat an option
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toogle switch for tWR (switch between 48 or fail safe variante ) 1=48 0=failsafe
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minimum tRAS49tRCDtRTP
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tRCD+tRTP3712
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optimum tRAS57tRCDtRTPBurstLength 16 / 2 = BurstChopX = + 2 or 4 Points, minimum = 0
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tRCD + tRTP + BurstChop + X371280
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safe tRAStCWLtRCDWRtWRthis variant garants always a ROW Hit
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tCWL+tRCDWR+tWR111263748
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tRC = tRAS, for safe tRAS
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tRC = for tRAS minimum or optimumtRC = for tRAS mintRC = for tRAS Optimum
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8694
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tFAW32for all of our DIMMs ~ 32.
32 for 1kb pagesize dimms
48 for 2kb pagesize dimms.
// As long as it is not confirmed that AMD uses 2 MC links each DIMM, the value is 32/48 instead of 16/24 :)
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tRFC
choose your clock value
and your tRFC for
your Dimm type
Hynix A-Die [ns]Hynix M-Die [ns]Samsung B-Die [ns]Samsung D-Die [ns]Micron A+G REV [ns]Micron Rev B [ns] if you stay with 65535 maxed, is 320,352,384,416
If you want to give 65528 a try , then its 308, 340, 372 ,404 ~
pick one that suits you Scale both sets +/- 32. But keep values.
Just test what REFI brings you most consistency(not latency)
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120160260270260360minimum value
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DDR5 MHz6400
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tRFC [tREFi 65528]500156,3156,3156,3156,3156,3156,3if you use tREFi 65528, red value=if you reach min Value
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tRFC [tREFi 65535]480150,0150,0150,0150,0150,0150,0if you use tREFi 65535, red value=if you reach min Value
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tRRD_S/DG8
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tRRD_L/SG12recommended 12
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tWTR_S/DG7Veii tweak (can also run at 4 )Thanks to this I have found a "small" exploit of my own.
DDR4 & DDR5 can execute within 2 writes per read.
Actually a little more, but they can do 2.

As an example:
RRDS 8
RRDL 12
WTRS 4
WTRL 24
RDRDSCL = 12-8+1 = 5

That is,
If CCDLWR is used and WTRL would be exactly double of RRDL (normal)
If the SC_Longs are also correct (the minimums) and RTP is not too low.
Then the loop ends at exactly the right time to run WTRS at half clock.
If not, a delay somewhere between reads would be too slow or too short.
tWR & tRTP as main variables.

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tWTR_L/SG24
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Interface Timings
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CCD_S8
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CCD_L=>tRRDL oder tRRDS 12
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CCDL_WR= CCDL *224
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Mathematical Offset Timings
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tRDRDSC_L min5CCDLRdBurstChopOdtEnDly
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CCDL - RdBurstChop + ODTEnDly1281
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tWRWRSC_L min17CCDLWRWrBurstChopOdtEnDly
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CCDLWR - WrBurstChop + ODTEnDly2481
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tRDWR min12tCLtCWLBurstChopOdtEnDlyWrPRE (shown in MemTweak) safety delay
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tCL - tCWL + BC8 + ODTEnDly + WrPRE + SafetyDly28268101
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Tertiäre Timings (SC + SD + DD)
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If you have single sided Module, then you have to enter value 1 (for example 2*16 GB),
if you have dual sided Modules
(Chips on both sides like 2*32GB) you have to enter the value 0
1_DD & _SD/DR wenn 2x32bit MC/DIMM
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tRDWR (lower 16 possible min formula above)12tCCD_S4not clear
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tWRRD 1tRDRD_4not clear
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tRDRDSC1tWRWR_3not clear
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tRDRDSD1tRDWR_8not clear
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tRDRDDD8tWRRD_2not clear
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tWRWRSC1
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tWRWRSD1
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tWRWRDD6
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tREFi < Maximum Value 65536(-1),
please choose lower Value if you have thermal problems		6553665536 (minus 8192 steps) = result -1.
// to choose for thermal problems
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tRRD_L/SG16GB Dimm24GB Dimm
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tCCD_S oder höher812
CCDS , or bigger. CCDS is
always 8 unless double MC link.
Starting point 8+
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Refresh TimingstRFC
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tRFC480you have to edit this value for calculate tRFC2+ tRFCsb
at the moment AMD doesn't apply these values
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tRFC2260
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tRFCsb212
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tWR FailsafetWRtCLtWTRLBuffer 8
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tWR = WTR_A+ RTP + X (BC8) ~ tCL+tWTRL+86028248
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 round up multiple of 660
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