Assertion Plan

	A	B	C	D	E	F
1	SI No.	Features	Signals	Scenarios	Description	Status
2	1	reset_assert	rst	RST=1	When RST is asserted the RES should be Z	Done
3	2	operand_wait	OPA, OPB, INP_VALID	INP_VALID=10/01, CMD=requires both operands	If the CMD value requires both operaands and input valid is 01/10 wait for a window of 1 to 16 cycles	Not started
4	3	invalid_inputs	CMD, INP_VALID	CMD= invalid or INP_VALID=00	When the inputs are invalid the outputs should be set to Z	Done
5	4	latch_outputs	CIN, RES, COUT, G,L,E	When CE=0	When CLK_EN is 0 the outputs latch on the previous values	Done
6	5	z_x_driven	MODE, INP_VALID, CE, OPA, OPB, CIN, CMD	MODE=X/Z, INP_VALID=X/Z, CE=X/Z, OPA=X/Z, OPB=X/Z, CIN=X/Z, CMD=X/Z	When the inputs are driven by Z/X	Not started
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