A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | AA | AB | AC | AD | AE | |
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1 | 0 | - Alias - | - Group - | - Encoding - | #S = immediate (I=1). S = register. #D = immediate (L=1). D = register. - Assembly Syntax - | * Z = (result == 0). ** If #S and cogex, PC += signed(S). If #S and hubex, PC += signed(S << 2). If S, PC = register S. - Description - | * +1 if crosses hub long - Cogex Cycles - | * +1 if crosses hub long - Hubex Cycles - | * Data not forwarded. - Register Write - | - Hub R/W - | - Stack R/W - | CF/ZF are local bits Dv = variable to write - Spin Methods - | |||||||||||||||||||

2 | 1 | . | Miscellaneous | 0000 0000000 000 000000000 000000000 | NOP | No operation. | 2 | same | |||||||||||||||||||||||

3 | 2 | . | Math and Logic | EEEE 0000000 CZI DDDDDDDDD SSSSSSSSS | ROR D,{#}S {WC/WZ/WCZ} | Rotate right. D = [31:0] of ({D[31:0], D[31:0]} >> S[4:0]). C = last bit shifted out if S[4:0] > 0, else D[0]. * | 2 | same | D | ROR_(Dv,S) | |||||||||||||||||||||

4 | 3 | . | Math and Logic | EEEE 0000001 CZI DDDDDDDDD SSSSSSSSS | ROL D,{#}S {WC/WZ/WCZ} | Rotate left. D = [63:32] of ({D[31:0], D[31:0]} << S[4:0]). C = last bit shifted out if S[4:0] > 0, else D[31]. * | 2 | same | D | ROL_(Dv,S) | |||||||||||||||||||||

5 | 4 | . | Math and Logic | EEEE 0000010 CZI DDDDDDDDD SSSSSSSSS | SHR D,{#}S {WC/WZ/WCZ} | Shift right. D = [31:0] of ({32'b0, D[31:0]} >> S[4:0]). C = last bit shifted out if S[4:0] > 0, else D[0]. * | 2 | same | D | SHR_(Dv,S) | |||||||||||||||||||||

6 | 5 | . | Math and Logic | EEEE 0000011 CZI DDDDDDDDD SSSSSSSSS | SHL D,{#}S {WC/WZ/WCZ} | Shift left. D = [63:32] of ({D[31:0], 32'b0} << S[4:0]). C = last bit shifted out if S[4:0] > 0, else D[31]. * | 2 | same | D | SHL_(Dv,S) | |||||||||||||||||||||

7 | 6 | . | Math and Logic | EEEE 0000100 CZI DDDDDDDDD SSSSSSSSS | RCR D,{#}S {WC/WZ/WCZ} | Rotate carry right. D = [31:0] of ({{32{C}}, D[31:0]} >> S[4:0]). C = last bit shifted out if S[4:0] > 0, else D[0]. * | 2 | same | D | RCR_(Dv,S) | |||||||||||||||||||||

8 | 7 | . | Math and Logic | EEEE 0000101 CZI DDDDDDDDD SSSSSSSSS | RCL D,{#}S {WC/WZ/WCZ} | Rotate carry left. D = [63:32] of ({D[31:0], {32{C}}} << S[4:0]). C = last bit shifted out if S[4:0] > 0, else D[31]. * | 2 | same | D | RCL_(Dv,S) | |||||||||||||||||||||

9 | 8 | . | Math and Logic | EEEE 0000110 CZI DDDDDDDDD SSSSSSSSS | SAR D,{#}S {WC/WZ/WCZ} | Shift arithmetic right. D = [31:0] of ({{32{D[31]}}, D[31:0]} >> S[4:0]). C = last bit shifted out if S[4:0] > 0, else D[0]. * | 2 | same | D | SAR_(Dv,S) | |||||||||||||||||||||

10 | 9 | . | Math and Logic | EEEE 0000111 CZI DDDDDDDDD SSSSSSSSS | SAL D,{#}S {WC/WZ/WCZ} | Shift arithmetic left. D = [63:32] of ({D[31:0], {32{D[0]}}} << S[4:0]). C = last bit shifted out if S[4:0] > 0, else D[31]. * | 2 | same | D | SAL_(Dv,S) | |||||||||||||||||||||

11 | 10 | . | Math and Logic | EEEE 0001000 CZI DDDDDDDDD SSSSSSSSS | ADD D,{#}S {WC/WZ/WCZ} | Add S into D. D = D + S. C = carry of (D + S). * | 2 | same | D | ADD_(Dv,S) | |||||||||||||||||||||

12 | 11 | . | Math and Logic | EEEE 0001001 CZI DDDDDDDDD SSSSSSSSS | ADDX D,{#}S {WC/WZ/WCZ} | Add (S + C) into D, extended. D = D + S + C. C = carry of (D + S + C). Z = Z AND (result == 0). | 2 | same | D | ADDX_(Dv,S) | |||||||||||||||||||||

13 | 12 | . | Math and Logic | EEEE 0001010 CZI DDDDDDDDD SSSSSSSSS | ADDS D,{#}S {WC/WZ/WCZ} | Add S into D, signed. D = D + S. C = correct sign of (D + S). * | 2 | same | D | ADDS_(Dv,S) | |||||||||||||||||||||

14 | 13 | . | Math and Logic | EEEE 0001011 CZI DDDDDDDDD SSSSSSSSS | ADDSX D,{#}S {WC/WZ/WCZ} | Add (S + C) into D, signed and extended. D = D + S + C. C = correct sign of (D + S + C). Z = Z AND (result == 0). | 2 | same | D | ADDSX_(Dv,S) | |||||||||||||||||||||

15 | 14 | . | Math and Logic | EEEE 0001100 CZI DDDDDDDDD SSSSSSSSS | SUB D,{#}S {WC/WZ/WCZ} | Subtract S from D. D = D - S. C = borrow of (D - S). * | 2 | same | D | SUB_(Dv,S) | |||||||||||||||||||||

16 | 15 | . | Math and Logic | EEEE 0001101 CZI DDDDDDDDD SSSSSSSSS | SUBX D,{#}S {WC/WZ/WCZ} | Subtract (S + C) from D, extended. D = D - (S + C). C = borrow of (D - (S + C)). Z = Z AND (result == 0). | 2 | same | D | SUBX_(Dv,S) | |||||||||||||||||||||

17 | 16 | . | Math and Logic | EEEE 0001110 CZI DDDDDDDDD SSSSSSSSS | SUBS D,{#}S {WC/WZ/WCZ} | Subtract S from D, signed. D = D - S. C = correct sign of (D - S). * | 2 | same | D | SUBS_(Dv,S) | |||||||||||||||||||||

18 | 17 | . | Math and Logic | EEEE 0001111 CZI DDDDDDDDD SSSSSSSSS | SUBSX D,{#}S {WC/WZ/WCZ} | Subtract (S + C) from D, signed and extended. D = D - (S + C). C = correct sign of (D - (S + C)). Z = Z AND (result == 0). | 2 | same | D | SUBSX_(Dv,S) | |||||||||||||||||||||

19 | 18 | . | Math and Logic | EEEE 0010000 CZI DDDDDDDDD SSSSSSSSS | CMP D,{#}S {WC/WZ/WCZ} | Compare D to S. C = borrow of (D - S). Z = (D == S). | 2 | same | D | CMP_(D,S) | |||||||||||||||||||||

20 | 19 | . | Math and Logic | EEEE 0010001 CZI DDDDDDDDD SSSSSSSSS | CMPX D,{#}S {WC/WZ/WCZ} | Compare D to (S + C), extended. C = borrow of (D - (S + C)). Z = Z AND (D == S + C). | 2 | same | CMPX_(D,S) | ||||||||||||||||||||||

21 | 20 | . | Math and Logic | EEEE 0010010 CZI DDDDDDDDD SSSSSSSSS | CMPS D,{#}S {WC/WZ/WCZ} | Compare D to S, signed. C = correct sign of (D - S). Z = (D == S). | 2 | same | CMPS_(D,S) | ||||||||||||||||||||||

22 | 21 | . | Math and Logic | EEEE 0010011 CZI DDDDDDDDD SSSSSSSSS | CMPSX D,{#}S {WC/WZ/WCZ} | Compare D to (S + C), signed and extended. C = correct sign of (D - (S + C)). Z = Z AND (D == S + C). | 2 | same | CMPSX_(D,S) | ||||||||||||||||||||||

23 | 22 | . | Math and Logic | EEEE 0010100 CZI DDDDDDDDD SSSSSSSSS | CMPR D,{#}S {WC/WZ/WCZ} | Compare S to D (reverse). C = borrow of (S - D). Z = (D == S). | 2 | same | CMPR_(D,S) | ||||||||||||||||||||||

24 | 23 | . | Math and Logic | EEEE 0010101 CZI DDDDDDDDD SSSSSSSSS | CMPM D,{#}S {WC/WZ/WCZ} | Compare D to S, get MSB of difference. C = MSB of (D - S). Z = (D == S). | 2 | same | CMPM_(D,S) | ||||||||||||||||||||||

25 | 24 | . | Math and Logic | EEEE 0010110 CZI DDDDDDDDD SSSSSSSSS | SUBR D,{#}S {WC/WZ/WCZ} | Subtract D from S (reverse). D = S - D. C = borrow of (S - D). * | 2 | same | D | SUBR_(Dv,S) | |||||||||||||||||||||

26 | 25 | . | Math and Logic | EEEE 0010111 CZI DDDDDDDDD SSSSSSSSS | CMPSUB D,{#}S {WC/WZ/WCZ} | Compare and subtract S from D if D >= S. If D => S then D = D - S and C = 1, else D same and C = 0. * | 2 | same | D | CMPSUB_(Dv,S) | |||||||||||||||||||||

27 | 26 | . | Math and Logic | EEEE 0011000 CZI DDDDDDDDD SSSSSSSSS | FGE D,{#}S {WC/WZ/WCZ} | Force D >= S. If D < S then D = S and C = 1, else D same and C = 0. * | 2 | same | D | FGE_(Dv,S) | |||||||||||||||||||||

28 | 27 | . | Math and Logic | EEEE 0011001 CZI DDDDDDDDD SSSSSSSSS | FLE D,{#}S {WC/WZ/WCZ} | Force D <= S. If D > S then D = S and C = 1, else D same and C = 0. * | 2 | same | D | FLE_(Dv,S) | |||||||||||||||||||||

29 | 28 | . | Math and Logic | EEEE 0011010 CZI DDDDDDDDD SSSSSSSSS | FGES D,{#}S {WC/WZ/WCZ} | Force D >= S, signed. If D < S then D = S and C = 1, else D same and C = 0. * | 2 | same | D | FGES_(Dv,S) | |||||||||||||||||||||

30 | 29 | . | Math and Logic | EEEE 0011011 CZI DDDDDDDDD SSSSSSSSS | FLES D,{#}S {WC/WZ/WCZ} | Force D <= S, signed. If D > S then D = S and C = 1, else D same and C = 0. * | 2 | same | D | FLES_(Dv,S) | |||||||||||||||||||||

31 | 30 | . | Math and Logic | EEEE 0011100 CZI DDDDDDDDD SSSSSSSSS | SUMC D,{#}S {WC/WZ/WCZ} | Sum +/-S into D by C. If C = 1 then D = D - S, else D = D + S. C = 1 if signed overflow. * | 2 | same | D | SUMC_(Dv,S) | |||||||||||||||||||||

32 | 31 | . | Math and Logic | EEEE 0011101 CZI DDDDDDDDD SSSSSSSSS | SUMNC D,{#}S {WC/WZ/WCZ} | Sum +/-S into D by !C. If C = 0 then D = D - S, else D = D + S. C = 1 if signed overflow. * | 2 | same | D | SUMNC_(Dv,S) | |||||||||||||||||||||

33 | 32 | . | Math and Logic | EEEE 0011110 CZI DDDDDDDDD SSSSSSSSS | SUMZ D,{#}S {WC/WZ/WCZ} | Sum +/-S into D by Z. If Z = 1 then D = D - S, else D = D + S. C = 1 if signed overflow. * | 2 | same | D | SUMZ_(Dv,S) | |||||||||||||||||||||

34 | 33 | . | Math and Logic | EEEE 0011111 CZI DDDDDDDDD SSSSSSSSS | SUMNZ D,{#}S {WC/WZ/WCZ} | Sum +/-S into D by !Z. If Z = 0 then D = D - S, else D = D + S. C = 1 if signed overflow. * | 2 | same | D | SUMNZ_(Dv,S) | |||||||||||||||||||||

35 | 34 | . | Math and Logic | EEEE 0100000 CZI DDDDDDDDD SSSSSSSSS | TESTB D,{#}S WC/WZ | Test bit S[4:0] of D, write to C/Z. C/Z = D[S[4:0]]. | 2 | same | TESTB_(D,S,WC/WZ) | ||||||||||||||||||||||

36 | 35 | . | Math and Logic | EEEE 0100001 CZI DDDDDDDDD SSSSSSSSS | TESTBN D,{#}S WC/WZ | Test bit S[4:0] of !D, write to C/Z. C/Z = !D[S[4:0]]. | 2 | same | TESTBN_(D,S,WC/WZ) | ||||||||||||||||||||||

37 | 36 | . | Math and Logic | EEEE 0100010 CZI DDDDDDDDD SSSSSSSSS | TESTB D,{#}S ANDC/ANDZ | Test bit S[4:0] of D, AND into C/Z. C/Z = C/Z AND D[S[4:0]]. | 2 | same | TESTB_(D,S,ANDC/ANDZ) | ||||||||||||||||||||||

38 | 37 | . | Math and Logic | EEEE 0100011 CZI DDDDDDDDD SSSSSSSSS | TESTBN D,{#}S ANDC/ANDZ | Test bit S[4:0] of !D, AND into C/Z. C/Z = C/Z AND !D[S[4:0]]. | 2 | same | TESTBN_(D,S,ANDC/ANDZ) | ||||||||||||||||||||||

39 | 38 | . | Math and Logic | EEEE 0100100 CZI DDDDDDDDD SSSSSSSSS | TESTB D,{#}S ORC/ORZ | Test bit S[4:0] of D, OR into C/Z. C/Z = C/Z OR D[S[4:0]]. | 2 | same | TESTB_(D,S,ORC/ORZ) | ||||||||||||||||||||||

40 | 39 | . | Math and Logic | EEEE 0100101 CZI DDDDDDDDD SSSSSSSSS | TESTBN D,{#}S ORC/ORZ | Test bit S[4:0] of !D, OR into C/Z. C/Z = C/Z OR !D[S[4:0]]. | 2 | same | TESTBN_(D,S,ORC/ORZ) | ||||||||||||||||||||||

41 | 40 | . | Math and Logic | EEEE 0100110 CZI DDDDDDDDD SSSSSSSSS | TESTB D,{#}S XORC/XORZ | Test bit S[4:0] of D, XOR into C/Z. C/Z = C/Z XOR D[S[4:0]]. | 2 | same | TESTB_(D,S,XORC/XORZ) | ||||||||||||||||||||||

42 | 41 | . | Math and Logic | EEEE 0100111 CZI DDDDDDDDD SSSSSSSSS | TESTBN D,{#}S XORC/XORZ | Test bit S[4:0] of !D, XOR into C/Z. C/Z = C/Z XOR !D[S[4:0]]. | 2 | same | TESTBN_(D,S,XORC/XORZ) | ||||||||||||||||||||||

43 | 42 | . | Math and Logic | EEEE 0100000 CZI DDDDDDDDD SSSSSSSSS | BITL D,{#}S {WCZ} | Bit S[4:0] of D = 0, C,Z = D[S[4:0]]. | 2 | same | D | BITL_(Dv,S) | |||||||||||||||||||||

44 | 43 | . | Math and Logic | EEEE 0100001 CZI DDDDDDDDD SSSSSSSSS | BITH D,{#}S {WCZ} | Bit S[4:0] of D = 1, C,Z = D[S[4:0]]. | 2 | same | D | BITH_(Dv,S) | |||||||||||||||||||||

45 | 44 | . | Math and Logic | EEEE 0100010 CZI DDDDDDDDD SSSSSSSSS | BITC D,{#}S {WCZ} | Bit S[4:0] of D = C, C,Z = D[S[4:0]]. | 2 | same | D | BITC_(Dv,S) | |||||||||||||||||||||

46 | 45 | . | Math and Logic | EEEE 0100011 CZI DDDDDDDDD SSSSSSSSS | BITNC D,{#}S {WCZ} | Bit S[4:0] of D = !C, C,Z = D[S[4:0]]. | 2 | same | D | BITNC_(Dv,S) | |||||||||||||||||||||

47 | 46 | . | Math and Logic | EEEE 0100100 CZI DDDDDDDDD SSSSSSSSS | BITZ D,{#}S {WCZ} | Bit S[4:0] of D = Z, C,Z = D[S[4:0]]. | 2 | same | D | BITZ_(Dv,S) | |||||||||||||||||||||

48 | 47 | . | Math and Logic | EEEE 0100101 CZI DDDDDDDDD SSSSSSSSS | BITNZ D,{#}S {WCZ} | Bit S[4:0] of D = !Z, C,Z = D[S[4:0]]. | 2 | same | D | BITNZ_(Dv,S) | |||||||||||||||||||||

49 | 48 | . | Math and Logic | EEEE 0100110 CZI DDDDDDDDD SSSSSSSSS | BITRND D,{#}S {WCZ} | Bit S[4:0] of D = RND, C,Z = D[S[4:0]]. | 2 | same | D | BITRND_(Dv,S) | |||||||||||||||||||||

50 | 49 | . | Math and Logic | EEEE 0100111 CZI DDDDDDDDD SSSSSSSSS | BITNOT D,{#}S {WCZ} | Bit S[4:0] of D = !bit, C,Z = D[S[4:0]]. | 2 | same | D | BITNOT_(Dv,S) | |||||||||||||||||||||

51 | 50 | . | Math and Logic | EEEE 0101000 CZI DDDDDDDDD SSSSSSSSS | ANDN D,{#}S {WC/WZ/WCZ} | AND !S into D. D = D & !S. C = parity of result. * | 2 | same | D | ANDN_(Dv,S) | |||||||||||||||||||||

52 | 51 | . | Math and Logic | EEEE 0101001 CZI DDDDDDDDD SSSSSSSSS | AND D,{#}S {WC/WZ/WCZ} | AND S into D. D = D & S. C = parity of result. * | 2 | same | D | AND_(Dv,S) | |||||||||||||||||||||

53 | 52 | . | Math and Logic | EEEE 0101010 CZI DDDDDDDDD SSSSSSSSS | OR D,{#}S {WC/WZ/WCZ} | OR S into D. D = D | S. C = parity of result. * | 2 | same | D | OR_(Dv,S) | |||||||||||||||||||||

54 | 53 | . | Math and Logic | EEEE 0101011 CZI DDDDDDDDD SSSSSSSSS | XOR D,{#}S {WC/WZ/WCZ} | XOR S into D. D = D ^ S. C = parity of result. * | 2 | same | D | XOR_(Dv,S) | |||||||||||||||||||||

55 | 54 | . | Math and Logic | EEEE 0101100 CZI DDDDDDDDD SSSSSSSSS | MUXC D,{#}S {WC/WZ/WCZ} | Mux C into each D bit that is '1' in S. D = (!S & D ) | (S & {32{ C}}). C = parity of result. * | 2 | same | D | MUXC_(Dv,S) | |||||||||||||||||||||

56 | 55 | . | Math and Logic | EEEE 0101101 CZI DDDDDDDDD SSSSSSSSS | MUXNC D,{#}S {WC/WZ/WCZ} | Mux !C into each D bit that is '1' in S. D = (!S & D ) | (S & {32{!C}}). C = parity of result. * | 2 | same | D | MUXNC_(Dv,S) | |||||||||||||||||||||

57 | 56 | . | Math and Logic | EEEE 0101110 CZI DDDDDDDDD SSSSSSSSS | MUXZ D,{#}S {WC/WZ/WCZ} | Mux Z into each D bit that is '1' in S. D = (!S & D ) | (S & {32{ Z}}). C = parity of result. * | 2 | same | D | MUXZ_(Dv,S) | |||||||||||||||||||||

58 | 57 | . | Math and Logic | EEEE 0101111 CZI DDDDDDDDD SSSSSSSSS | MUXNZ D,{#}S {WC/WZ/WCZ} | Mux !Z into each D bit that is '1' in S. D = (!S & D ) | (S & {32{!Z}}). C = parity of result. * | 2 | same | D | MUXNZ_(Dv,S) | |||||||||||||||||||||

59 | 58 | . | Math and Logic | EEEE 0110000 CZI DDDDDDDDD SSSSSSSSS | MOV D,{#}S {WC/WZ/WCZ} | Move S into D. D = S. C = S[31]. * | 2 | same | D | MOV_(Dv,S) | |||||||||||||||||||||

60 | 59 | . | Math and Logic | EEEE 0110001 CZI DDDDDDDDD SSSSSSSSS | NOT D,{#}S {WC/WZ/WCZ} | Get !S into D. D = !S. C = !S[31]. * | 2 | same | D | NOT_(Dv,S) | |||||||||||||||||||||

61 | 60 | alias | Math and Logic | EEEE 0110001 CZ0 DDDDDDDDD DDDDDDDDD | NOT D {WC/WZ/WCZ} | Get !D into D. D = !D. C = !D[31]. * | 2 | same | D | NOT_(Dv) | |||||||||||||||||||||

62 | 61 | . | Math and Logic | EEEE 0110010 CZI DDDDDDDDD SSSSSSSSS | ABS D,{#}S {WC/WZ/WCZ} | Get absolute value of S into D. D = ||S. C = S[31]. * | 2 | same | D | ABS_(Dv,S) | |||||||||||||||||||||

63 | 62 | alias | Math and Logic | EEEE 0110010 CZ0 DDDDDDDDD DDDDDDDDD | ABS D {WC/WZ/WCZ} | Get absolute value of D into D. D = ||D. C = D[31]. * | 2 | same | D | ABS_(Dv) | |||||||||||||||||||||

64 | 63 | . | Math and Logic | EEEE 0110011 CZI DDDDDDDDD SSSSSSSSS | NEG D,{#}S {WC/WZ/WCZ} | Negate S into D. D = -S. C = MSB of result. * | 2 | same | D | NEG_(Dv,S) | |||||||||||||||||||||

65 | 64 | alias | Math and Logic | EEEE 0110011 CZ0 DDDDDDDDD DDDDDDDDD | NEG D {WC/WZ/WCZ} | Negate D. D = -D. C = MSB of result. * | 2 | same | D | NEG_(Dv) | |||||||||||||||||||||

66 | 65 | . | Math and Logic | EEEE 0110100 CZI DDDDDDDDD SSSSSSSSS | NEGC D,{#}S {WC/WZ/WCZ} | Negate S by C into D. If C = 1 then D = -S, else D = S. C = MSB of result. * | 2 | same | D | NEGC_(Dv,S) | |||||||||||||||||||||

67 | 66 | alias | Math and Logic | EEEE 0110100 CZ0 DDDDDDDDD DDDDDDDDD | NEGC D {WC/WZ/WCZ} | Negate D by C. If C = 1 then D = -D, else D = D. C = MSB of result. * | 2 | same | D | NEGC_(Dv) | |||||||||||||||||||||

68 | 67 | . | Math and Logic | EEEE 0110101 CZI DDDDDDDDD SSSSSSSSS | NEGNC D,{#}S {WC/WZ/WCZ} | Negate S by !C into D. If C = 0 then D = -S, else D = S. C = MSB of result. * | 2 | same | D | NEGNC_(Dv,S) | |||||||||||||||||||||

69 | 68 | alias | Math and Logic | EEEE 0110101 CZ0 DDDDDDDDD DDDDDDDDD | NEGNC D {WC/WZ/WCZ} | Negate D by !C. If C = 0 then D = -D, else D = D. C = MSB of result. * | 2 | same | D | NEGNC_(Dv) | |||||||||||||||||||||

70 | 69 | . | Math and Logic | EEEE 0110110 CZI DDDDDDDDD SSSSSSSSS | NEGZ D,{#}S {WC/WZ/WCZ} | Negate S by Z into D. If Z = 1 then D = -S, else D = S. C = MSB of result. * | 2 | same | D | NEGZ_(Dv,S) | |||||||||||||||||||||

71 | 70 | alias | Math and Logic | EEEE 0110110 CZ0 DDDDDDDDD DDDDDDDDD | NEGZ D {WC/WZ/WCZ} | Negate D by Z. If Z = 1 then D = -D, else D = D. C = MSB of result. * | 2 | same | D | NEGZ_(Dv) | |||||||||||||||||||||

72 | 71 | . | Math and Logic | EEEE 0110111 CZI DDDDDDDDD SSSSSSSSS | NEGNZ D,{#}S {WC/WZ/WCZ} | Negate S by !Z into D. If Z = 0 then D = -S, else D = S. C = MSB of result. * | 2 | same | D | NEGNZ_(Dv,S) | |||||||||||||||||||||

73 | 72 | alias | Math and Logic | EEEE 0110111 CZ0 DDDDDDDDD DDDDDDDDD | NEGNZ D {WC/WZ/WCZ} | Negate D by !Z. If Z = 0 then D = -D, else D = D. C = MSB of result. * | 2 | same | D | NEGNZ_(Dv) | |||||||||||||||||||||

74 | 73 | . | Math and Logic | EEEE 0111000 CZI DDDDDDDDD SSSSSSSSS | INCMOD D,{#}S {WC/WZ/WCZ} | Increment with modulus. If D = S then D = 0 and C = 1, else D = D + 1 and C = 0. * | 2 | same | D | INCMOD_(Dv,S) | |||||||||||||||||||||

75 | 74 | . | Math and Logic | EEEE 0111001 CZI DDDDDDDDD SSSSSSSSS | DECMOD D,{#}S {WC/WZ/WCZ} | Decrement with modulus. If D = 0 then D = S and C = 1, else D = D - 1 and C = 0. * | 2 | same | D | DECMOD_(Dv,S) | |||||||||||||||||||||

76 | 75 | . | Math and Logic | EEEE 0111010 CZI DDDDDDDDD SSSSSSSSS | ENCOD D,{#}S {WC/WZ/WCZ} | Get bit position of top-most '1' in S into D. D = {27'b0, 5'position}. C = (S == 0). * | 2 | same | D | ENCOD_(Dv,S) | |||||||||||||||||||||

77 | 76 | alias | Math and Logic | EEEE 0111010 CZ0 DDDDDDDDD DDDDDDDDD | ENCOD D {WC/WZ/WCZ} | Get bit position of top-most '1' in D into D. D = {27'b0, 5'position}. C = (S == 0). * | 2 | same | D | ENCOD_(Dv) | |||||||||||||||||||||

78 | 77 | . | Miscellaneous | EEEE 0111011 CZI DDDDDDDDD SSSSSSSSS | <empty> D,{#}S {WC/WZ/WCZ} | <empty> | |||||||||||||||||||||||||

79 | 78 | . | Math and Logic | EEEE 0111100 CZI DDDDDDDDD SSSSSSSSS | TESTN D,{#}S {WC/WZ/WCZ} | Test D with !S. C = parity of (D & !S). Z = ((D & !S) == 0). | 2 | same | TESTN_(D,S) | ||||||||||||||||||||||

80 | 79 | . | Math and Logic | EEEE 0111101 CZI DDDDDDDDD SSSSSSSSS | TEST D,{#}S {WC/WZ/WCZ} | Test D with S. C = parity of (D & S). Z = ((D & S) == 0). | 2 | same | TEST_(D,S) | ||||||||||||||||||||||

81 | 80 | alias | Math and Logic | EEEE 0111101 CZ0 DDDDDDDDD DDDDDDDDD | TEST D {WC/WZ/WCZ} | Test D. C = parity of D. Z = (D == 0). | 2 | same | TEST_(D) | ||||||||||||||||||||||

82 | 81 | . | Math and Logic | EEEE 0111110 CZI DDDDDDDDD SSSSSSSSS | ANYB D,{#}S {WC/WZ/WCZ} | Check if any bits set in either D or S. C = parity of (D | S). Z = ((D | S) == 0). | 2 | same | ANYB_(D,S) | ||||||||||||||||||||||

83 | 82 | . | Miscellaneous | EEEE 0111111 CZI DDDDDDDDD SSSSSSSSS | <empty> D,{#}S {WC/WZ/WCZ} | <empty> | |||||||||||||||||||||||||

84 | 83 | . | Math and Logic | EEEE 100000N NNI DDDDDDDDD SSSSSSSSS | SETNIB D,{#}S,#N | Set S[3:0] into nibble N in D, keeping rest of D same. | 2 | same | D | SETNIB_(Dv,S,N) | |||||||||||||||||||||

85 | 84 | alias | Math and Logic | EEEE 1000000 00I 000000000 SSSSSSSSS | SETNIB {#}S | Set S[3:0] into nibble established by prior ALTSN instruction. | 2 | same | D | ||||||||||||||||||||||

86 | 85 | . | Math and Logic | EEEE 100001N NNI DDDDDDDDD SSSSSSSSS | GETNIB D,{#}S,#N | Get nibble N of S into D. D = {28'b0, S.NIBBLE[N]). | 2 | same | D | GETNIB_(Dv,S,N) | |||||||||||||||||||||

87 | 86 | alias | Math and Logic | EEEE 1000010 000 DDDDDDDDD 000000000 | GETNIB D | Get nibble established by prior ALTGN instruction into D. | 2 | same | D | ||||||||||||||||||||||

88 | 87 | . | Math and Logic | EEEE 100010N NNI DDDDDDDDD SSSSSSSSS | ROLNIB D,{#}S,#N | Rotate-left nibble N of S into D. D = {D[27:0], S.NIBBLE[N]). | 2 | same | D | ROLNIB_(Dv,S,N) | |||||||||||||||||||||

89 | 88 | alias | Math and Logic | EEEE 1000100 000 DDDDDDDDD 000000000 | ROLNIB D | Rotate-left nibble established by prior ALTGN instruction into D. | 2 | same | D | ||||||||||||||||||||||

90 | 89 | . | Math and Logic | EEEE 1000110 NNI DDDDDDDDD SSSSSSSSS | SETBYTE D,{#}S,#N | Set S[7:0] into byte N in D, keeping rest of D same. | 2 | same | D | SETBYTE_(Dv,S,N) | |||||||||||||||||||||

91 | 90 | alias | Math and Logic | EEEE 1000110 00I 000000000 SSSSSSSSS | SETBYTE {#}S | Set S[7:0] into byte established by prior ALTSB instruction. | 2 | same | D | ||||||||||||||||||||||

92 | 91 | . | Math and Logic | EEEE 1000111 NNI DDDDDDDDD SSSSSSSSS | GETBYTE D,{#}S,#N | Get byte N of S into D. D = {24'b0, S.BYTE[N]). | 2 | same | D | GETBYTE_(Dv,S,N) | |||||||||||||||||||||

93 | 92 | alias | Math and Logic | EEEE 1000111 000 DDDDDDDDD 000000000 | GETBYTE D | Get byte established by prior ALTGB instruction into D. | 2 | same | D | ||||||||||||||||||||||

94 | 93 | . | Math and Logic | EEEE 1001000 NNI DDDDDDDDD SSSSSSSSS | ROLBYTE D,{#}S,#N | Rotate-left byte N of S into D. D = {D[23:0], S.BYTE[N]). | 2 | same | D | ROLBYTE_(Dv,S,N) | |||||||||||||||||||||

95 | 94 | alias | Math and Logic | EEEE 1001000 000 DDDDDDDDD 000000000 | ROLBYTE D | Rotate-left byte established by prior ALTGB instruction into D. | 2 | same | D | ||||||||||||||||||||||

96 | 95 | . | Math and Logic | EEEE 1001001 0NI DDDDDDDDD SSSSSSSSS | SETWORD D,{#}S,#N | Set S[15:0] into word N in D, keeping rest of D same. | 2 | same | D | SETWORD_(Dv,S,N) | |||||||||||||||||||||

97 | 96 | alias | Math and Logic | EEEE 1001001 00I 000000000 SSSSSSSSS | SETWORD {#}S | Set S[15:0] into word established by prior ALTSW instruction. | 2 | same | D | ||||||||||||||||||||||

98 | 97 | . | Math and Logic | EEEE 1001001 1NI DDDDDDDDD SSSSSSSSS | GETWORD D,{#}S,#N | Get word N of S into D. D = {16'b0, S.WORD[N]). | 2 | same | D | GETWORD_(Dv,S,N) | |||||||||||||||||||||

99 | 98 | alias | Math and Logic | EEEE 1001001 100 DDDDDDDDD 000000000 | GETWORD D | Get word established by prior ALTGW instruction into D. | 2 | same | D | ||||||||||||||||||||||

100 | 99 | . | Math and Logic | EEEE 1001010 0NI DDDDDDDDD SSSSSSSSS | ROLWORD D,{#}S,#N | Rotate-left word N of S into D. D = {D[15:0], S.WORD[N]). | 2 | same | D | ROLWORD_(Dv,S,N) |