AubCPU3 ISA

	A	B	C	D	E	F	G	H	I	J	K	L	M	N	O	P	Q	R	S	T	U	V	X	Y	AA	AB
1		Mnemonic	Description	Format		Format	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	Register	Use	Address Range	Use
2	0	HLT	Halt	H		A	-				Src2				Src1/Dest				Opcode				x0	Hardwire zero	0-15	I/O
3	1	JIN	Jump Immediate If Not Zero	G		B	-				Ptr				Dest				Opcode				x1	Return Value	16-255	RAM
4	2	CMP	Compare	A		C	-				Ptr				Src				Opcode				x2	Arg A
5	3	ADD	Add	A		D	-				-				Src/Dest				Opcode				x3	Arg B
6	4	SUB	Subtract	A		E	-				Src				Dest				Opcode				x4	Arg C
7	5	AND	Bitwise And	A		F	Immediate								Dest				Opcode				x5	General
8	6	ORR	Bitwise Or	A		G	Instruction Address								-				Opcode				x6	General
9	7	XOR	Bitwise Exclusive Or	A		H	-				-				-				Opcode				x7	General
10	8	LSH	Logical Left Shift	D	Not needed																		x8	General
11	9	RSH	Logical Right Shift	D																			x9	General
12	10	INC	Increment	D																			x10	General
13	11	DEC	Decrement	D																			x11	General
14	12	LOD	Load	B																			x12	General
15	13	LDI	Load Immediate	F																			x13	Flags
16	14	STO	Store	C																			x14	Stack Ptr
17	15	CPR	Copy Register	E																			x15	PC
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