Buzzwords

	A	C	D	E	F	G	H	I	J	K	L	M	N	O	P	Q	R	S	T	U	V	W	X	Y	Z	AA	AB	AC	AD	AE	AF
1	Dates:	8/25	8/30	9/1	9/8	9/13	9/15	9/20	9/22	9/27	9/29	10/4	10/6	10/11	10/13	10/18	10/20	10/25	10/27	11/1	11/3	11/8	11/10	11/15	11/17	11/22	11/24	11/29	12/01
2	Scribes:	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael	Ali/Sabee	Jason/Adeel	Ying-Wei/Michael
3		High-level language	Abstraction	Positional Notation	ASCII Code	Hexadecimal	One-Hot Encoding	Clock cycle	State	Address Space	Addressability	Sign-extend	OS/IO Space	Predicate	Exam	Assembler	High Level Language	Initialization	Stack Underflow/Overflow	Linked List	Tradeoff	Privilege	Echo (a character)	Control Signal	Exam	TRAP routine	Thanksgiving	Access Control Violation (ACV)	Donald Knuth
4		Low-level language	Hardware	Integer Conversion Binary to Decimal	1's Compliment	Binary	Mux (Multiplexer)	Write Enable (WE)	Combinational Logic	MAR	Program Counter (PC)	Steering bit	Operates	Iteration (decomposition)		LDR	Low Level Language	Von Neumann	Subroutine	Access	Recursion	Priority	newline character	Gated		TRAP vector table		Trap Table	The Art of Programming
5		Algorithm	Software	Fraction Conversion Binary to Decimal	String (characters)	Decimal	Decoder	Gated Latch	Sequential Logic	MDR	Instruction Register	Instruction Cycle	Data Movement	File		LDI	Assembler	Assembler	JSR/JSRR	Update	Stack	PSR	ASCII control codes	Bus		Interrupt vector table		Trap Vector
6		definitive-ness (algorithm property)	Tradeoffs	Range of numbers represented by n bits	Opcode (instruction)	Transistor	Adder	Cross-coupling (latch)	Finite State Machine	Moore Machine	Compiler	Data Path (Microarchitecture)	Control	End-of-Text Character (EOT)		STR	Compiler	first pass	Return	Struct	R6 (Stack Pointer)	RTI		Load		System stack		Interrupt Enable Bit
7		effective-ness (algorithm property)	Computer System	Crossing Boundary (Overflow)	Logical Operator (AND, NOT, etc.)	Richard Feynman	Sum & Carry bit	Computer Memory	State Transition	Memory Address vs Contents	Assembler	Bus	Trap / System Call / OSH (Operating System Help)	Trap Vector		STI	Assembly Language	symbol table	JMP	Link	Tail End Recursion	SSP		Data path		User stack		Polling
8		finite-ness (algorithm property)	Central Processing Unit (CPU)	Binary Addition	Input Combinations (truth table)	N-type transistor	Programmable Logic Array (PLA)	Giga-byte (GB)	Clock	Computation Unit	Machine Language	Gate (Bus data)	Loop Body	Base Register (LDR/STR)		State Machine	Abstraction	second pass	Linkage	Character String	Iterative Algorithm	USP		Clock Cycle		RTI (return from trap or interrupt)		Device Priority
9		Assembly language	Microprocessor	Sign Extension	Demorgan's law	P-type transistor	R-S Latch	Address (location in memory)	Input	Registers (Temporary Storage)	Word (16–bit in LC–3)	Control Signal	For / While			Control Signals	Opcode	data type	Library	Null Terminated	Recursive Algorithm	IO		setCC		Privileged instruction		Interrupt Vector
10		ISA (Instruction Set Architecture)	Memory	Bit Vector	Bit-wise operation	Transistor gate	Set/Reset	Word-line	Output	I/O	Fetch	Arithmetic Logic Unit (ALU)	Iteration			Exclusive Signals	Operands	data structure	Caller	Binary Search	Maze Problem	KBSR		SEXT
11		micro-architecture	I/O (Input/Output)	Logical Variable	Exclusive OR (XOR)	Closed Switch	Quiescent State	Bit-line	Asynchronous	Control Unit	Instruction Cycle	Branch Enable	Initialization			Set NZP	Labels	stack/lifo	Callee	Sequential storage		KBDR		ZEXT
12		Transistor	Disk	Unary Operator	Equivalence Operator (EQ)	Positive Battery Terminal	Feedback	Memory Address Register (MAR)	Synchronous		Memory READY signal						Comments	fifo/queue	Save/Restore	Scan opcode (x86)		DSR
13			Peripherals	NOT (FLIP)	NAND	Negative Battery Terminal		Memory Data Register (MDR)	Clock		Source Register						Decimal, #	push		Recursion		DDR
14			Moore's Law	Truth Table	NOR	Ground		Register	Flip flop		Destination Register						Hex, x	pop		Factorial		Interrupt vs. Polling
15			Transistor	AND (ALL)	Carry bit (adjusting 1's complement result)	Vdd		Address Space	master slave flip flop		Condition Code (NZP)						Binary, b	stack pointer (sp/R6)		Fibonacci		Memory Mapped I/O
16			Nanometer	OR (ANY)	CRAY computers	0/1/Floating		Addressability			Offset (PC+Offset)						Pseudo-Ops	stack growth		Iterative
17			Pins		Fraction	Inverter/Not/Compliment		State			Evaluate Address						.FILL			Basis Test (Base Case)
18			Data type(s)		Exponent	Mux (Multiplexer)					Branch Instruction						.BLKW
19			2's Compliment		Significand	Decoder					Immediate value
20			Bit Vector		Sign bit	Adder
21			Subtration/Multplication/Division using ADD		Single vs. Double precision floating point (32 vs. 64 bit)	Storage
22			ASCII Code		Bias/Excess (in floating point exponent)
23			Voltage		Infinitiy value (floating point representation)
24			Binary Digit (Bit)		Nan (Not A Number)
25			Decimal Digit		Operating System
26			x86 ISA
27			Floating Point Numbers
28			Sign and Magnitude
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