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Revision DateChange Description
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5/8/2018Alinged on 260p connector.
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5/8/2018
remove hbled signal. Will keep this onboard mezzanine. Instead will use BOOT_IND#, active low signal indicating SOC has booted.
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5/8/2018lowered UART total interfaces to 4x. 2x of them have RTS/CTS signals
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Fixed the 1.8v eSPI or 3.3v for LPC
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added net vbus sense and fixed net names, took away from a GPIO. USB2APWREN_GPIO
USB2BVBUSSNS_GPIO
USB2AVBUSSNS_GPIO
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5/14/2018Changed net names to better describe net names
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5/14/2018Changed two UART primary flow control signals to secondary function for GPIOS
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6/12/2018Fixed netname priority for GPIO_RGMIIMDC and GPIO_RGMIIMDIO to have GPIO come first
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6/13/2018Removed 2nd JTAG interface.
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6/13/2018Moved USB host and USB device into its own general function for general pin count tab
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6/13/2018Changed USB host net name from USB2AVBUSSNS to USB2AOC (Over current)
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6/13/2018Reduced UARTs from 5 to 3. Moved the 4 extra signals to GPIO
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6/13/2018Changed a UART netname to "CONSOLE" instead of UART
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6/13/2018Increased to 16 I2C bus's. 4 are now secondary function instead of GPIOs.
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6/14/2018Added quad mode support for both FW SPI and SPI1 interface. SIO[0:3] support as secondary function
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6/15/2018Fix net naming errors for 1GbT signals
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6/18/2018IO0/MOSI and IO1/MISO per standard - switched the SPI SIGNALS
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6/21/2018
Changed a few descriptions, updated SIOPWREQ to SIOPME. Swapped PECI signals (wrong descriptions; only these were swapped)
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7/4/2018Added column for runBMC aspeed naming on schematic
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7/5/2018Removed reset from PWRGD. This is an input only for monitoring PSUs
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7/5/2018SIO netnames need to have a "#" to reflect active low
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8/14/2018Removed active low "#" for INDICATOR
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8/14/2018Changed pinout reordering
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8/14/2018INDICATOR is secondary option instead of primary
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8/14/2018BMC_RST_N_CONN to BMC_RESET#
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8/14/2018Add secondary function for KLUDGE as GPIO
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8/14/2018Addended the net names that had VDD with _STBY
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8/15/2018Moved Indicator to pin 109
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8/15/2018SIOPWREQ was actualyl SIPME#
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8/15/2018
229, 231, and 241, 243 pins were swapped due to routing concenrs. Planning to swap these back for consitency.
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9/17/2018
For SYSSPI signals we have made these primary function (GPIO is second function). The Indicator and WP signals have been moved
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9/26/2018
Added secondary functions for GPIOs. These will be UARTS (RX, TX). Pins 144, 146, 148, 150 are updated on pinout. Pinout namings also updated
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10/2/2018
Removed secondary functionality for FWSPI pins; now act as FWSPI only (no GPIO secondary or primary function)
RGMIIRXCK for connector no longer has GPIO functionality
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10/18/2018Added pinout for MiniSAS HD Connector on BUV
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11/15/2018
Changed Pin 2 from VDD_1V8_STBY to VDD_IO_REF. This is now an output voltage used for reference i/o, low current
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11/15/2018Updated the direction for the pinout naming tab.
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11/15/2018Changed USB2A primary descrioption as host
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11/15/2018Changed USB net names to include HD (host) and D (Device) to be more descriptive
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11/15/2018Changed BMCLPC3V3_BMCESPI1V8 to VDD_LPC3V3_ESPI1V8
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11/15/2018
For runBMC_v2_260p_sodimm_pinouts, for System SPI, added IO0 to MOSI and IO1 to MISO (these changes were in the pinout naming but not in the sodimm pinout)
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11/15/2018
Added System SPI pins to the runBMC_pinout_naming sheet (they were missing before), 4 GPIOs were removed
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11/15/2018Added UART3 & UART4 TX&RX pins, removed 4 GPIOs
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11/15/2018Removed hardware flow control for UART1 & UART2, 4 GPIOs were added
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11/15/2018Removed SIOPME signal, 1 GPIO added
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11/15/2018
Renamed "Primary" and "Secondary" to "Function 1" and "Function 2", since we are now describing two types of pins; dedicated function and dual function
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11/15/2018ADC [8-15] is GPI only.
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11/15/2018
Changing the following GPIOs to GPO's only. GPIO_SPI1_IO2, SYSMISO_GPIO, SYSMOSI_GPIO, SPI1MISO_GPIO, SPI1MOSI_GPIO, UART1TX_GPIO to only be GPO
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11/15/2018Back annotation of runBMC_v2_260p_sodimm_pinouts to make sure GPIOs are in ascending order
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11/29/2018Change PECI pin to have no alternate functionality (on General Pin Count tab)
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11/29/2018
I2C13 is connected to ID FRU, so I2C13 should not be dual function. Updated General Pin Count Tab & runBMC_pinout_naming tab
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11/29/2018Removed SIOONCTRL from General Pin Count & runBMC_pinout_naming
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12/8/2019Added GPIO as 2nd function for RGMIIRXCK
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12/8/2019Removed duplicate UARTs in GPIOI blocks for UART3 and UART4
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12/8/2019Added clear description for USB host/device pinout description
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1/9/2019Changed VDD_IO_REF netname to VDD_RGMII_REF
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1/10/2019Locked Revision 1.0!!
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2/21/2019UNLOCKED
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2/21/2019Changed some color scheming in the runBMC_v2_260p_sodimm_pinouts tab to be higher contrast
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4/15/2019Changed Kludge to CPU_RST#. CPU_RST# is the PCH reset or AMD/CPLD reset output
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5/7/2019Changed Klugde_GPIO65 to RESERVED_GPIO65. Removed Kludge language
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8/6/2019
Added Pass-Through pins to some GPIOs, I2C9 is now the interal FRU bus. This means GPIOs had to be incremented by 2, change on pins 47 to 183
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8/6/2019Locked Revision 1.4
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1/24/2021Draft of v1.5
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1/24/2021Added new tab for v1.5 pinout proposal and changelist discussion
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1/24/2021Change pin name from CPU_RST# to PLT_RST#
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1/24/2021Add pin95(GPIO63) to be BMC_PWRGD(output)
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1/24/2021Add one more reset input pin on pin93(GPIO61) as PFR_RST#
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1/24/2021Add SD interface (pin 141,143,187,189,199,201,48,50)
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1/24/2021Add I3C interace (pin 123,125,205,207,128,130,134,136)
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1/25/2020Updated Changelist Discussion Tab
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