ABCDEFGHIJKLMNOPQR
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MnemonicOperandCyclesSZHP/VNCIFF1IFF2M1M2M3M4M5M6Group
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ADC A,(HL) / n 07* * * v 0* Math
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ADC A,r 04* * * v 0* Math
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ADC HL,rr 15* * ? v 0* Math
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ADD A,(HL) / n 07* * * v 0* Math
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ADD A,(ix+n) 19* * * v 0* Math
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ADD A,r 04* * * v 0* Math
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ADD HL,rr 11v * x 0* Math
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ADD ii,rr 15 x 0* Math
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AND (HL) / n 07* * 1P 00 Logical
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AND (ii+n) 19* * 1P 00 Logical
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AND r 04* * 1P 00 Logical
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BIT b,(HL) 12x * 1x 0 Bitwise
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BIT b,(ii+n) 20x * 1x 0 Bitwise
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BIT b,r 08x * 1x 0 Bitwise
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CALL nn / cc,nn 17 / 10 Flow
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CCF 04 x 0* Internal
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CP (HL) / n 07* * * v 1* Math
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CP (ix+n) 19* * * v 1* Math
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CP r 04* * * v 1* Math
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CPD 16* * * * 1 Math
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CPDR 21 / 16 * * * * 1 Block
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CPI 16* * * * 1 Math
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CPIR 21 / 16 * * * * 1 Block
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CPL 04 1 1 Internal
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DAA 04* * * P * Math
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DEC (HL) 11* * * v 1 Math
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DEC (ii+n) 23* * * v 1 Math
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DEC ix 10 Internal
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DEC r 04* * * v 1 Math
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DEC rr 06 Internal
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DI 04 0 Internal
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DJNZ n 13 / 8 Flow
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EI 04 1 Internal
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EX (SP),ix 23 Exchange
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EX AF,AF' 04 Exchange
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EX DE,HL 04 Exchange
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EX SP,HL 04 Exchange
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EXX 04 Exchange
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HALT 04 Flow
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IM x 08 Flow
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IN A,(n) 11 Port I/O
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IN r,(C) 12* * * P 0 Port I/O
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INC (HL) 11 Math
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INC (ix+n) 23 Math
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INC ix 10 Internal
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INC r 04 Math
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INC rr 06 Internal
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IND / INI 16 Port I/O
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INDR / INIR 21 / 16 Block
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JP cc,nn 10 / 10 Flow
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JP HL 04 Flow
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JP ix 08 Flow
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JP nn 10 Flow
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JR cc,n 12 / 7 Flow
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JR n 12 Flow
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LD (ix+n),r / n 19 Store
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LD (nn),A 13 Store
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LD (nn),HL 16 Store
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LD (nn),rr 20 Store
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LD (rr),r 07 Store
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LD A,(nn) 13 Fetch
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LD A,I / R 09 IFF1 Load
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LD HL,(nn) 16 Fetch
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LD I,A / R,A 09 Load
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LD ix,nn 14 Load
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LD r,(ix+n) 19 Fetch
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LD r,(rr) 07 Fetch
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LD r,n 07 Fetch
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LDr,RLC(ix+n)Undocumented
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LD r,r 04 Load
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LD rr,(nn) 20 Fetch
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LD rr,nn 10 Load
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LD SP,HL 06 Load
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LD SP,ix 10 Load
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LDD / LDI 16 Block
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LDDR / LDIR 21 / 16 Block
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NEG 08 Logical
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NOP 04 Internal
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OR (ix+n) 19 Logical
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OR n 07 Logical
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OR r 04 Logical
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OTDR / OTIR 21 / 16 Block
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OUT (C),n / r 12 Port I/O
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OUT (n),A 11 Port I/O
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OUTD / OUTI 16 Block
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POP ix 14 Fetch
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POP rr 10 Fetch
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PUSH ix 15 Store
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PUSH rr 11 Store
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RES b,(HL) 15 Bitwise
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RES b,(ix+n) 23 Bitwise
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RES b,r 08 Bitwise
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LDr,RES(ix+n)Undocumented
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RET 10 Flow
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RET cc 11 / 5 Flow
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RETI 14 Flow
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RETN 14 IFF2 Flow
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RLA / RRA 04 Shift
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RLCA / RRCA 04 Shift