Calculation of CPU_LOAD_PERCENT

	A	B	C	D	E	F	G
1	Calculation of:=
2	#define CPU_LOAD_PERCENT 16CLK_PHASES((390625*4096)/FREQOSC)
3
4	UDB TYPE	CLOCK TYPE	FREQOSC	CLK_PHASES	CALCULATED CPU_LOAD_PERCENT	Existing HARD CODED VALUE	Calculation agrees with code
5	UDB3	Chrystal	16000000	4	6400	6400	Yes
6		FRC8X	58982400	4	1736.111111	1744	No, but close
7	UDB4	Chrystal	32000000	2	1600	1600	Yes
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9	The above calculations are currently being questioned ....
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11
12	Check calculations in light of Guilio's comments
13	dspic family reference manual makes clear that timer clock is using Fosc / 2 i.e. Fcy and not the Chrystal speed directly .... the following is for the UDB4 driven from the Chystal ...
14	Chrystal speed	Fcy	Timer 5 set to interrupt at....	_cpu_timer at full load (theoretical) per second	New CPU LOAD PERCENT
15	32000000	16000000	4096	3906.25	1677.7216
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18	Note: I've used the word theoretical above as Timer 5 is priority 6, and the Servo Out PWM generator is at priority 7.
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20	dspic 33F family reference manual, chapter on timers :-
21	http://ww1.microchip.com/downloads/en/DeviceDoc/70205D.pdf
22
23	Setting up of T5 timer:-
24	http://code.google.com/p/gentlenav/source/browse/trunk/libUDB/background.c#122
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26
27	NEW NOTE:
28	PDH 2/7/2012	I have measure the maximum CPU load emprically. With the standard code of MatrixPilot a maxed out CPU will show as 95% cpu load currently.
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30		This is because on a UDB4, the CPU_LOAD_PERCENT should actually be 1677 and not 1600. This difference explains the 5% cpu load shortfall.
31		So the current CPU_LOAD_PERCENT of 1600, in matrixpilot is approximately correct.
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