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Nor Gate

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Partially based on csg.csail.mit.edu/6.884/handouts/lectures/L03-CMOS-Gates.pdf‎

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2-Input Nor Logic Gate

How is it build using PMOS and NMOS transistors?

How would you size the NMOS transistors

(to get approx. the same fall time as an inverter)?

PMOS same rise time as inverter?

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NOR Gate

  • When both A and B are low, output is high
  • When either A or B is high, output is low

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NAND or NOR? Which is preferable?

NAND

NOR

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2-input OR Logic Gate (internals)

Connect the output of a NOR to a NOT Gate

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NOR Gate Simulations

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Objective

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  • Simulate the timing of a NOR gate

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